AM2434: Boot setup for AM2434

Hi,

Please refer to this page which explains how to resolve this kind of errors.

Data Verification Errors

Thanks,

Hi Kowshik,

Thank you for your prompt response.

I have followed the link referred by you, but still i am not able to debug.

Now its in debug stage but partially, i am not able to get in to loopback state of "fsi_loopback_polling_am243x_evm_r5ffss0" example.

Please find the attached image and linker.cmd file for reference.

/* This is the stack that is used by code running within main()
 * In case of NORTOS,
 * - This means all the code outside of ISR uses this stack
 * In case of FreeRTOS
 * - This means all the code until vTaskStartScheduler() is called in main()
 *   uses this stack.
 * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
 */
--stack_size=16384
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
 * This is also the heap used by pvPortMalloc in FreeRTOS
 */
--heap_size=32768
-e_vectors  /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */

/* This is the size of stack when R5 is in IRQ mode
 * In NORTOS,
 * - Here interrupt nesting is disabled as of now
 * - This is the stack used by ISRs registered as type IRQ
 * In FreeRTOS,
 * - Here interrupt nesting is enabled
 * - This is stack that is used initally when a IRQ is received
 * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
 * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
 */
__IRQ_STACK_SIZE = 256;
/* This is the size of stack when R5 is in IRQ mode
 * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
 */
__FIQ_STACK_SIZE = 256;
__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
__ABORT_STACK_SIZE = 256;  /* This is the size of stack when R5 is in ABORT mode */
__UNDEFINED_STACK_SIZE = 256;  /* This is the size of stack when R5 is in UNDEF mode */

SECTIONS
{
    /* This has the R5F entry point and vector table, this MUST be at 0x0 */
    .vectors:{} palign(8) > R5F_VECS

    /* This has the R5F boot code until MPU is enabled,  this MUST be at a address < 0x80000000
     * i.e this cannot be placed in DDR
     */
    GROUP {
        .text.hwi: palign(8)
        .text.cache: palign(8)
        .text.mpu: palign(8)
        .text.boot: palign(8)
        .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
    } > MSRAM

    /* This is rest of code. This can be placed in DDR if DDR is available and needed */
    GROUP {
        .text:   {} palign(8)   /* This is where code resides */
        .rodata: {} palign(8)   /* This is where const's go */
    } > MSRAM

    /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
    GROUP {
        .data:   {} palign(8)   /* This is where initialized globals and static go */
    } > MSRAM

    /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
    GROUP {
        .bss:    {} palign(8)   /* This is where uninitialized globals go */
        RUN_START(__BSS_START)
        RUN_END(__BSS_END)
        .sysmem: {} palign(8)   /* This is where the malloc heap goes */
        .stack:  {} palign(8)   /* This is where the main() stack goes */
    } > MSRAM

    /* This is where the stacks for different R5F modes go */
    GROUP {
        .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
        RUN_START(__IRQ_STACK_START)
        RUN_END(__IRQ_STACK_END)
        .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
        RUN_START(__FIQ_STACK_START)
        RUN_END(__FIQ_STACK_END)
        .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
        RUN_START(__SVC_STACK_START)
        RUN_END(__SVC_STACK_END)
        .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
        RUN_START(__ABORT_STACK_START)
        RUN_END(__ABORT_STACK_END)
        .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
        RUN_START(__UNDEFINED_STACK_START)
        RUN_END(__UNDEFINED_STACK_END)
    } > MSRAM

    /* Sections needed for C++ projects */
    GROUP {
        .ARM.exidx:  {} palign(8)   /* Needed for C++ exception handling */
        .init_array: {} palign(8)   /* Contains function pointers called before main */
        .fini_array: {} palign(8)   /* Contains function pointers called after main */
    } > MSRAM

    /* General purpose user shared memory, used in some examples */
    .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
    /* this is used when Debug log's to shared memory are enabled, else this is not used */
    .bss.log_shared_mem  (NOLOAD) : {} > LOG_SHM_MEM
    /* this is used only when IPC RPMessage is enabled, else this is not used */
    .bss.ipc_vring_mem   (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
    /* General purpose non cacheable memory, used in some examples */
    .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
}

/*
NOTE: Below memory is reserved for DMSC usage
 - During Boot till security handoff is complete
   0x701E0000 - 0x701FFFFF (128KB)
 - After "Security Handoff" is complete (i.e at run time)
   0x701F4000 - 0x701FFFFF (48KB)

 Security handoff is complete when this message is sent to the DMSC,
   TISCI_MSG_SEC_HANDOVER

 This should be sent once all cores are loaded and all application
 specific firewall calls are setup.
*/

MEMORY
{
    R5F_VECS  : ORIGIN = 0x00000000 , LENGTH = 0x00000040
    R5F_TCMA  : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
    R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000

    /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
    NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000

    /* when using multi-core application's i.e more than one R5F/M4F active, make sure
     * this memory does not overlap with other R5F's
     */
    MSRAM     : ORIGIN = 0x70080000 , LENGTH = 0x40000

    /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
     * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
     */
    FLASH     : ORIGIN = 0x60100000 , LENGTH = 0x80000

    /* shared memory segments */
    /* On R5F,
     * - make sure there is a MPU entry which maps below regions as non-cache
     */
    USER_SHM_MEM            : ORIGIN = 0x701D0000, LENGTH = 0x180
    LOG_SHM_MEM             : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
    RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
}

Please help me out, what wrong i have done.

--

Thanks & Regards,

Divyesh Patel

Hi Divyesh,

It seems like you're loading a code that is compiled for the r5_0_0 core into the r50_1 core which doesn't work. Can you ensure you're loading in the correct core?

Thanks

Hi Kowshik,

Its correct,first i made mistake but later loaded it correctly in r5_0_0 core.

Actually i have custom board and i think my issue is related to following link

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1131350/am2434-load-program-error-during-board-bring-up/4202882?tisearch=e2e-sitesearch&keymatch=am2434%2525252520%2525252520DDR#4202882

I have made booting selection as "01111011" for BOOT7-0 & "00000010" for BOOT15-8 and followed above link. During this process my code stuck in the system initialization function.

First  i think, i need to load initialization script then i can debug my code.

If it is right, could you please provide me the correct sequence to load it correctly.

Please also verify my booting configuration.

--

Thanks & Regards,

Divyesh Patel

Hi Divyesh,

The boot mode option you shared seems to be not matching to any of the one's that are documentd. Can you please put it No Boot mode and run the dmsc.js script which initializes the core and then can you try to load your code into r50_0?

Thanks

Hi Kowshik,

In this configuration, i am unable to connect processor and getting following error.

I am using XDS110 JTAG for the debugging.

--

Thanks & Regards,

Divyesh Patel

Hi Divyesh,

In that mode, you have to first run the dmsc.js script present in the SDK to first initialize your SoC. you cannot directly connect to the r5 cores. Please follow this command and page to run the dmsc script.

AM243x MCU+ SDK: EVM Setup (ti.com)

Once this script runs, you should be able to connect to the R5 cores.

Thanks,

G Kowshik

Hi Kowshik,

In my case, its trying to connect with M3.

--

Thanks & Regards,

Divyesh Patel

Hi Divyesh, 

What Target configuration are you using please? Yes, the dmsc core is suppossed to connect to the M3 core, however it is not doing that because your target confiugration might be wrong.

Hi Sir,

Kowshik Gudimetla said:

What Target configuration are you using please?

Its AM243x ALV

--

Thanks & Regards,

Divyesh Patel

Hi Kowshik,

I am getting another error, please check it and help me out.

Please help me out.

--

Thanks & Regards,

Divyesh Patel

Hi Divyesh,

I have assigned this thread to our expert on AM243x, he'll be handling it.

Thanks,
G Kowshik

Hi Ming,

Thank you for message.

Ming Wei said:

The work around is after your power up the board, you may need to unplug and plug the JTAG.

I tried this way also but still getting same issue

Is there any mistake i have done?

Please guide me.

--

Thanks & Regards,

Divyesh Patel

Hi Divyesh,

Are you using the "NO BOOT" mode? 

Best regards,

Ming

Hi Ming,

Ming Wei said:

Are you using the "NO BOOT" mode? 

Yes, I am using same configuration.

--

Thanks & Regards,

Divyesh Patel

Hi Divyesh, 

Can you try to change the "Board or Device" in your target configuration from AM2434_ALV to AM243x_GP_EVM?

The other thing you can try is to use latest MCU+ SDK 08.05.00.

Best regards,

Ming

Hi Ming,

Yeah, Its working now.

But, Why its not working with AM243x_ALV? Is it bug? or some wrong procedure i have followed?

--

Thanks & Regards,

Divyesh Patel

Hi Ming,

Thank you so much for your support.

One last query regarding this is, is it fine to use EVM configuration?

Or i need to find cause and set as ALV

—

Thanks & Regards,

Divyesh Patel

Hi Ming,

Thank you so much for your support.

Your support is really helping me.

I am closing this thread.

—

Thanks & Regards,

Divyesh Patel