TMS570LC4357-EP: Asynchronous Reset cause

The CPU executes 32-bit word-aligned ARM instructions in ARM state. The CPU executes 32-bit and 16-bit halfword-aligned Thumb instruction in Thumb state. From your snapshots, I believe that the Thumb is used in your project: the instructions are 16-bit aligned, and T bit (5th) of SPSR is set..

So the address of instruction that has the prefetch abort is R14_abt - 0x4, and for data abort the address is R14_abt - 0x8. In your snapshot, it is pop instruction which causes the data abort: pop  {r4, r5, r6}

The instructions PUSH and POP always use the sp register for the base address. What is the value of SP register?

The ECC on TCM is always enabled. Is the BTCM (SRAM) is initialized before using it? Because the ECC check is done on the read operation (for example POP) and the ECC calculation is done on the write operation ( for example PUSH). A read operation from ECC protected BTCM with an uninitialized ECC code will always give you Data abort.

The ECC data of SRAM (BTCM) is located in the memory starting at 0x08400000.

Please check if ECC data at 0x08400000 + value of SP is correct for data in r4 and r5 registers.

The stack size can be changed from HALCoGen GUI.