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TMS570LS1227: DMA hardware request behavior with AIM

Mark Li
Prodigy 138 points
Part Number: TMS570LS1227

Hi,

Reference manual SPNU515C is unclear about the functionality of DMA AIM.  In section 16.2.8 it writes:

When Auto-initiation Mode (AIM) bit of Channel Control Register (Section 16.3.2.4) is enabled for a channel and the channel is triggered by a software request for a block transfer, the channel will restart again using the same channel information stored at the respective control packet after one block transfer is completed. In the case of Hardware Request, the channel needs to be retriggered each time after a block is complete even if auto-initiation is enabled.

However, in section 16.3.1.4 it writes:

The corresponding hardware enable bit is cleared automatically for the following conditions:

• At the end of a block transfer if the auto-initiation bit AIM (see CHCTRL) is not active.

• If an AHB bus error is detected for an active channel.

It seems like the second section is saying that AIM=1 will prevent the hardware enable bit from being cleared, but the first section is saying that AIM=1 will NOT prevent the hardware enable bit from being cleared.  Which section is correct?

  • +1
    TI__Guru 70621 points

    Hi Mark,

    I would say both the sections describing different information, I just rephase the information for you.

    16.3.1.4
    If AIM is not active, then HWCHENA bit is cleared at the end of the block transfer.
    If AIM is active, then HWCHENA bit will not get cleared at the end of the block transfer.

    16.2.8
    If AIM is enabled and channel is triggered by software, then the channel will be restart again using same channel information after block transfer completed.
    If AIM is enabled and channel is triggered by hardware, then the channel will not restart again after block transfer, and it should need to be retriggered.

    The section 16.3.1.4 is describing about HWCHENA bit and while the section 16.2.8 is describing about trigger behavior.

     For proper hardware trigger operation, first we have to enable HWCHENA bit, and we can optionally enable or disable the AIM.

    For example,

    HWCHENA=1 and AIM=1:

           In this case, if hardware trigger comes as usual first block of data will get transmitted as HWCHENA=1 and as AIM is also active here so the HWCHENA bit will not get cleared that means the next hardware trigger can also initiate another block of transfer and this keep continuous with each hardware trigger.

    HWCHENA=1 and AIM=0:

          In this case, if hardware trigger comes as usual first block of data will get transmitted as HWCHENA=1 and as AIM is not active here the HWCHENA bit will get cleared that means the next hardware trigger cannot initiate another block of transfer. In this case to initiate block transfer for hardware trigger then we have to reenable HWCHENA.

    HWCHENA=0

    In this case, irrespective of AIM bit no trigger will get initiates the block transfer.

    --

    Thanks & Regards<
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 138 points

    Hi Jagadish,

    I think that makes sense.  So if the channel has AIM=1 and software trigger enabled, the DMA transaction will be automatically repeated without trigger until it is disabled?  

  • 0 in reply to Mark Li
    TI__Guru 70621 points

    Hi Mark,

    Mark Li said:
    So if the channel has AIM=1 and software trigger enabled, the DMA transaction will be automatically repeated without trigger until it is disabled?  

    Yes, you are correct.

    --

    Thanks,

    Jagadish.