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TMS570LC4357: DMA FIFO/PORT A-B automatic change issue

GUILLERMO JARA
Prodigy 135 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hi,

I am developing a code where DMA is used for receiving transactions arriving to the SCI peripheral.

The program normally works during a couple of minutes but in the end it gets stuck.

Debugging It, it is observed that when this occurs the FIFO (sometimes called port in the spnu563a and in CCS) has changed from A to B. (During nominal operation portb registers in pink, including trfcount, is at 0s)

From my understanding the program does not make that FIFO change, moreover I don't know if it is possible to do that somehow.

Also, there is a bit of mixing in the naming convention for those registers as in CCS appear as in the image above but in the spu563 are referred more as FIFO than as PORT although sometimes are mixed those words too.

I don't know if there could be an explanation for this behaviour, that is for changing from PORT/FIFO A to B automatically or if there is a way to avoid it or there is a way to make it back to FIFO/PORT A.

Many thanks in advance and regards.

  • 0
    TI__Guru 69811 points

    Hi Guillermo,

    Is your code sharable?

    If it is sharable then it would be easy for us to debug your issue at our end.

    --

    Thanks & Regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 135 points

    Hi Jagadish,

    I am afraid I can not share the code but I can answer any specific question about it if you have any guess.

    I am finding pretty difficult to debug the problem, but I think that my main doubt is that: why a dma trasnfer that is always using FIFO A associated registers (FAACSADDR, FAACDADDR and FAACTC) changes to FIFO B associated register at some point? and, is this controllable?

    Thanks again and kind regards,

    Guillermo.

  • 0 in reply to GUILLERMO JARA
    TI__Guru 69811 points

    Hi Guillermo,

    I would say this change could happen, because as we are reading data from peripheral registers and moving that data to the SRAM memory(buffers) right.

    for this we will do PORTB read, and PORTA write for DMA configuration.

    The change you are mentioning might be due to this.

    Can you try to refer SCI DMA example in HALCoGen once?

    --

    Thanks & Regards,

    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 135 points

    Hi again Jagadish,

    Firstly thanks for your reply.

    The use of FIFO A or B doesn't seem to be related, in my experience, to the type of memory of the transactions which is related with PORTs. The user reference manual mixes the terms FIFO and PORT in a way that I think it misleads the understanding of the matter.

    What seems to be related to the change of the FIFO is the current use of the DMA. So if a transaction is currently happening and another, from a different DMA channel, is issued that seems to use the FIFO not in used. The only thing I have found related with this is: 

    But my question was more in the direction of controlling which FIFO will be used in order to know which FXACTC register to look. I could check the FXACDADDR or FXACSADDR but If possible I would've liked to avoid it.

    Thanks again and kind regards.

  • 0 in reply to GUILLERMO JARA
    TI__Guru 69811 points

    Hi Guillermo,

    GUILLERMO JARA said:
    But my question was more in the direction of controlling which FIFO will be used in order to know which FXACTC register to look. I could check the FXACDADDR or FXACSADDR but If possible I would've liked to avoid it.

    I go through the DMA chapter completely again and i don't see anything to control DMA's FIFO's. What i understand is it gets controlled automatically by DMA. The only thing we can control here is "bypass" FIFO.

    We can configure the FIFO in bypass mode, so that switching latency between the cannels gets reduced using this mode. In this mode the arbitration of channels carried out at source granularity, that means if the channel is configured for 8bit transfer then arbitration can be happen at every 8bit DMA transfer.

    --

    Thanks & Regards,
    Jagadish.