TMS570LC4357: S25FL256LAGNFM010 SPI Mode Doesn't Match

Ibrahim Aydin

Part Number: TMS570LC4357

Hello;

We are using an S25FL256LAGNFM010 NOR FLASH chip to store some data with TMS570LC4357. We can erase and store data through mibspi4 but we must use a clock phase with a normal clock. The documentation of the chip clearly says that we must use mode 0 (normal clock - no phase). What can cause such an anomaly?

Here is the chip's documentation:

https://www.infineon.com/dgdl/Infineon-S25FL256L_S25FL128L_256-MB_(32-MB)_128-MB_(16-MB)_3.0_V_FL-L_FLASH_MEMORY-DataSheet-v09_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ed40e335224&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files

Have a nice day

Sincerly.

İbrahim Aydın

over 2 years ago

0 QJ Wang over 2 years ago

TI__Guru**** 197306 points

For Phase=0, polarity=0, the SPI data is output on the rising edge of SPICLK, and the input data is latched on the falling edge.

If phase=1, the data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges, and the input data is latched on the rising edge of SPICLK.

Please double check the timing diagram of the flash datasheet

0 QJ Wang over 2 years ago in reply to QJ Wang

TI__Guru**** 197306 points

Flash:

For the two modes supported by this flash, the input data into the device is always latched in on the rising edge of the SCK signal and the output data is always available from the falling edge of the SCK clock signal.

For TMS570 SPI, Mode 1 (phase=1, polarity=0):

The data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges, and the input data is latched on the rising edge of SPICLK.

Thiis is why SPI mode 1 has to be used.

Arm-based microcontrollers

Arm-based microcontrollers forum

TMS570LC4357: S25FL256LAGNFM010 SPI Mode Doesn't Match