TMS570LC4357: ESM high interrupt not triggering

Magnus Aronsson

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hi,

I have set up a simple project using halcogen:

mibspi1 activated with "Enable Ram ECC" selected
het1[27] pin configured as output (connected to LED on devkit board)
ESM Chan 17 (mibspi1 ECC double error) is enabled, set to high level (FIQ) and set to affect nError pin
I have verified in the code that generated system initialisations are called att startup - they are added by default to enty point _c_int00
I have added calls to mibspiInit() and hetInit() to main()

I have managed to trip the mibspi1 double ECC error by setting the ECCDIAG_EN option in ECCDIAG_CTRL register for mibspi1 and manipulating the ECC values. This causes The correct flags to be set by ESM and the LED connected to nError lights up on the board.

What I want to test is to trap execution in the esmHighInterrupt() operation, however the interrupt does not appear to occur. I have added a "while(1)" to the interrupt operation, as well as setting the het1[27] LED (confirmed working), but this has no effect - execution continues normally.

What is missing from this configuration?

Regards,

Magnus

over 2 years ago

0 QJ Wang over 2 years ago

TI__Guru**** 196566 points

Hi Magnus,

I will check. Are the ECC error flags (ESM and MibSPI ECC) set?

0 QJ Wang over 2 years ago in reply to QJ Wang

TI__Guru**** 196566 points

How did you inject a 2-bit ECC error to MibSPI RAM?

0 Magnus Aronsson over 2 years ago in reply to QJ Wang

Prodigy 45 points

Yes, UERR_FLG0 of PAR_ECC_STAT is set, as well as bit/channel 17 of ESMSR1.

0 Magnus Aronsson over 2 years ago in reply to QJ Wang

Prodigy 45 points

To cause the uncorrectable ECC error I do the following:

Enable EDD Diagnostic mode for MIBSPI1 by setting bits ECCDIAG_EN(0-3) = 5h , in ECCDIAG_CTRL register for MIBSPI1
Set a value in SPI1 txRAM 0xFF0E0000, currently using value 0x0005A5A5
Set some value in ECC position for that RAM, address 0xFF0E0000 + 0x400, using value 0x0AAA5A5A
Perform read from the txRAM

+1 QJ Wang over 2 years ago in reply to Magnus Aronsson

TI__Guru**** 196566 points

Magnus Aronsson said:
ESM Chan 17 (mibspi1 ECC double error) is enabled, set to high level (FIQ) and set to affect nError pin

Is the nERROR pin asserted? By default the CPU FIQ is not enabled, have you enabled it before injecting EC error to MibSPI RAM?

There are three "gates" before an interrupt request gets to the CPU:

The module that generates an interrupt request has a register to enable each interrupt that it can generate.
The Vectored Interrupt Manager (VIM) has registers to allow an interrupt request from a module to be forwarded to the CPU as per the priority scheme (lower channel number first).
Finally the CPU itself must be configured to respond to the interrupt requests forwarded by the VIM (IRQ or FIQ).

0 Magnus Aronsson over 2 years ago in reply to QJ Wang

Prodigy 45 points

This was my mistake. I thought the interrupt enable was included in the systemInit() operation generated by halcogen.

Works as expected now - much appreciated!

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TMS570LC4357: ESM high interrupt not triggering