Hello,
We are attempting to use the PMU CPU cycle counter to implement a high-resolution timer in our code. Knowing that the register is only 32-bits, and with a CPU frequency of 300MHz, we have calculated that the counter will overflow in ~14 seconds. We have successfully implemented an extension of the counter to 64 bits by checking for overflow and incrementing a second 32-bit variable counter. However, this overflow detection check is done in the function that retrieves the current cycle counter. We would prefer to have a more controlled scheme for overflow detection.
While doing some digging, I found the following E2E forum post about an unrelated PMU artifact. In this post, QJ Wang made a comment about re-starting the cycle counter in the "PMU counter overflow interrupt routine". This interrupt would be highly preferable for us to use in order to increment our extended cycle counter. I have been reading the TMS570 documentation to try and see how to set this up, and have unfortunately uncovered very little information in the TRM or device datasheet. The only information that I have been able to find is that interrupt request 22 is for the "Cortex-R5F PMU Interrupt", but after configuring a project to set up this interrupt I never saw an occurrence of it triggering.
Is there a document available which describes the workings of the PMU, or could somebody please describe to me how to configure interrupts for PMU overflows?
Thank you,
James
