AM2434: EtherCAT ‘core’ that gets loaded onto the PRU, documentation

Adding this as well:

Allied to this question is what does the code that is on the R5 core expect in terms of pin maps?

Possible candidates might be the PHY RESET lines, the interrupt line from the PHYs back to the AM2434

Hi Jorgen,

JLA said:

The EtherCAT ‘core’ that gets loaded onto the PRU must expect certain signals to be on certain GPO pins. Is this documented in any place?

I would like to clarify here that, we do not have ethercat core. Also while ethercat firmware is running on PRU, Signals are expected on MII pins not on GPIO pins.

JLA said:

Although I can copy other designs – there are differences between them – and I’d like to understand what the requirements are exactly.

Can you point me to this info?

What are you referring to here as other design? Cold you please clarify that, it helps help me in enabling you with required info.

BR

Nilabh A.