LP-AM243: How to configure GPIO Event trigger for BCDMA operation

Bolt Hsieh

Part Number: LP-AM243

Hi experts,

I used AM243x's launch pad to test BCDMA. I can find SW trigger demo from SDK, but I don't know how to change SW trigger to HW trigger that is SW5 - GPIO54 of launch pad.

SW trigger SDK : https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/latest/exports/docs/api_guide_am243x/EXAMPLES_DRIVERS_UDMA_SW_TRIGGER.html

I know the knowledge from TRM that is L2G has GPIO event, but I don't know how to map the L2G - GPIO event to global trigger0 or global trigger1 of TR15-Type.

Please provide me the setting step to complete the BCDMA appliction of GPIO SW trigger.

Best Regards

Bolt

over 2 years ago

0 Frank Livingston over 2 years ago

TI__Mastermind 29388 points

Hi Bolt,

I'm looking into this and will get back with you.

Regards,
Frank

0 Frank Livingston over 2 years ago

TI__Mastermind 29388 points

Hi Bolt,

Sorry for the delay, I'm still looking into this.

Regards,
Frank

0 Haley Alexander over 2 years ago

TI__Intellectual 1465 points

Hi Bolt,

While Frank is looking into the application, can you look at section 11.1.4.16 of the TRM?

It shows steps for a packet transmission using Type 15. If it doesn't help, can you please tell us more about the use case? Particularly on the type of operation or transmission you are interested in.

Thanks,

Haley

0 Bolt Hsieh over 2 years ago in reply to Haley Alexander

Prodigy 110 points

Hi Haley,

Thanks for your response, but the section doesn't describe that how to set the hardware trigger (ex. GPIO-Input ) to global trigger 0 or 1.

So, I still don't know the knowledge of " GPIO Input control BCDMA work".

When I read the section, I had a new question.

The description of the steps : 1-b & 1-c says the reload function will be enable when the reload-enable sets to 1.

Does the reload function represent that BCDMA will restart when BCDMA was already done once?

If my description is right, how do I set the reload enable and offset ?

By the way, my operation of BCDMA reload was using dequeue & queue again for the same TR. The method spent a lot of time( about 7us ), so I want to use the reload funtion to reduce the dequeue & queue setting time.

Best Regards
Bolt

0 Bolt Hsieh over 2 years ago in reply to Frank Livingston

Prodigy 110 points

Hi Frank,

Thanks for your inform.

I still wait for a solution of your help.

Best Regards,
Bolt

0 Frank Livingston over 2 years ago in reply to Bolt Hsieh

TI__Mastermind 29388 points

Hi Bolt,

Sorry for the long delay on this. I'm pursuing this internally and will get back with you shortly.

Regards,
Frank

0 Haley Alexander over 2 years ago in reply to Frank Livingston

TI__Intellectual 1465 points

Hi Bolt,

Thanks for looking at the TRM section and giving more details. I can help you with the TRM questions.

Reload Enable is set to 1 if the Reload Count is non-zero, and Reload Count is described in 11.1.3.2.3 Transfer Request Descriptor.
The Reload function BCDMA loop through the Transfer Request (TRs) in the descriptor. So it is the equivalent of a descriptor that is (Reload_count)*(Last Entry - reload_index + 1) + (Last Entry + 1)
The above two point can help when you have some TRs run the first time and then repeat the same set of TRs X many times. You can set reload count and reload index to only loop on the repeating TRs and ignore the first TR.

I'll follow up with Frank on your questions about the triggers.

Best,

Haley

0 Bolt Hsieh over 2 years ago in reply to Haley Alexander

Prodigy 110 points

Hi Haley,

Thanks for your reply.

Using your reply, I knew that "Reload Count" = 0x1FF is an infinite loop for repeating TR.

But I cannot match the format of Table11-32 "Transfer Request Packet Descriptor Word0" to Table11-31 "Transfer Request Packet Descriptor Layout".

Hence, I failed to modify App_udmaTrpdInit() to reload the TR again.

So I don't know how to implement the function in my program. Can you give me some suggestions or an example for reference?

Thanks a lot.

Best Regards,

Bolt

0 Frank Livingston over 2 years ago in reply to Bolt Hsieh

TI__Mastermind 29388 points

Hi Bolt,

One approach for the GPIO trigger would be to take a GPIO interrupt on a CPU core and execute a BCDMA SW trigger inside the GPIO ISR. Would this approach work for you or do you need the direct hardware trigger?

Regards,
Frank

0 Bolt Hsieh over 2 years ago in reply to Frank Livingston

Prodigy 110 points

Hi Frank,

Thanks for your response,

But I want to direct hardware trigger BCDMA operation, the CPU can focus on doing other things.

The CPU can ignore the start set of BCDMA operation. Hence, the CPU just waits for the completion of BCDMA operation.

So, I still want to know how to set the GPIO HW trigger to the BCDMA's event trigger.

Best Regards,

Bolt

0 Frank Livingston over 2 years ago in reply to Bolt Hsieh

TI__Mastermind 29388 points

Hi Bolt,

Ok, thanks for the feedback. I'm continuing to pursue the direct HW trigger approach.

Regards,
Frank

0 Bolt Hsieh over 2 years ago in reply to Haley Alexander

Prodigy 110 points

Hi Haley,

About infinite repeatly use BCDMA of the same TR, can you give me some suggest?

If I need to create a new topic to ask this question. Please, let me know.

Thanks a lot

Best Regards,

Bolt

0 Haley Alexander over 2 years ago in reply to Bolt Hsieh

TI__Intellectual 1465 points

Hi Bolt,

Yes, please make a new topic. It will be easier to track the question that way as the HW trigger discussion will obscure it.

Thanks,

Haley

0 Frank Livingston over 2 years ago in reply to Bolt Hsieh

TI__Mastermind 29388 points

Hi Bolt,

Sorry for taking so long to respond concerning the GPIO trigger.

I was able to get the GPIO trigger to BCDMA transfer working on the AM243x-LP. I've shared the example code below. The example is based on SDK 08.05.

You were correct there is a path from GPIOMUX_INTRTR0 Outputs to the Interrupt Aggregator L2G Inputs. This can be gleaned from different sections of the TRM, e.g.:

Figure 10-56. SoC Time Sync Architecture : shows path from GPIOMUX_INTRTR0 to DMASS
Section 11.2.1.2.5 DMSS L2G Interrupt Inputs : shows mapping of GPIOMUX_INTRTR0 Outputs to Interrupt Aggregator (L2G) Inputs

Looking at the DMSS L2G Interrupt Inputs table, I decided to use GPIOMUX_INTRTR0 Output 16 to L2G Input 24.

I had to modify the RM board configuration as described here: https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/08_05_00_24/exports/docs/api_guide_am243x/RESOURCE_ALLOCATION_GUIDE.html. Specifically, I had to assign GPIOMUX_INTRTR0 Output 16 to the Interrupt Aggregator. I've attached the updated file below.

After updating the configuration, I had to rebuild the board configuration, etc., as described here: https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/08_05_00_24/exports/docs/api_guide_am243x/TOOLS_SYSFW.html#BOARCFG_GEN

I used SBL NULL on the LP, so I had to rebuild SBL NULL using this build command (not correctly shown in docs):

gmake -s -C examples/drivers/boot/sbl_null/am243x-lp/r5fss0-0_nortos/ti-arm-clang all PROFILE=release

Next, I reflashed the LP using the procedure documented here: https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/08_05_00_24/exports/docs/api_guide_am243x/EVM_SETUP_PAGE.html#autotoc_md26

On the LP, I decided to use the push-button connected to GPIO1_54. This is mapped to GPIO bank interrupt 3 (floor(54/16)=3).

Looking at the TISCI docs:

https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am64x/interrupt_cfg.html#main-gpiomux-introuter0-interrupt-router-input-sources: GPIO Bank Int 3 is connected to GPIO IR Input 183 => source index 93.
https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am64x/interrupt_cfg.html#main-gpiomux-introuter0-interrupt-router-output-destinations: GPIO IR Output 16 is connected to L2G Input 24 => destination index 24.

For the L2G configuration, the correct DMASS0_INTAGGR_0_INTAGGR_L2G register needs to be written. Please see the TRM,11.2.4.4.1.10 DMASS0_INTAGGR_0_MAP Register.

For local event j, the register address is: 0x48120000 + (j * 0x20U)
For local event 24 (Input from GPIOMUX_INTRTR0 Output 16), this would be: 0x48120000 + (24 * 0x20U).

I got the following description from an internal UDMA expert on what should be written to this register:

Looking at this particular case the customer should set the register they are highlighting to the value of the BCDMA channel he is using *2 + 50176 + the trigger number. The 50176 comes from table 11-59 in the TRM for BCDMA triggers. Global trigger 0 would be this value and global trigger 1 would be this value + 1. Where the channel number would be the ring that the TR is on from table 11-63.

So if he wants to trigger a block copy channel 5 with global trigger 1 the value would be 50176+2*(5)+1 = 50187.
If he wants to trigger RX channel 5 with global trigger 0 the value would be 50176 + 2*(48) + 5 + 0 = 50272.

The example code uses BCDMA Ch 12 and Trigger 0, so the value written is: 50176+2*(12)+0 = 50200.

The function App_udmaTrpdInit() configures BCDMA to perform a 1-D transfer upon receiving the trigger.

The example triggers a transfer for each press of LP SW5, which is connected to GPIO1_54. GPIO interrupt status is checked to determine when a trigger has occurred. After this, the source & destination buffers are compared.

Please let me know if have an questions or concerns.

Regards,
Frank

/cfs-file/__key/communityserver-discussions-components-files/908/gpio_5F00_trigger_5F00_bcdma_5F00_am243x_2D00_lp_5F00_r5fss0_2D00_0_5F00_nortos_5F00_ti_2D00_arm_2D00_clang.zip

/cfs-file/__key/communityserver-discussions-components-files/908/5873.sciclient_5F00_defaultBoardcfg_5F00_rm.c

0 Bolt Hsieh over 2 years ago in reply to Frank Livingston

Prodigy 110 points

Hi Frank,

Thanks for your response and solution.

Because I have another research topic now, I will try it later.

If I have any new information, I will respond soon.

Thanks a lot.

Best Regards,

Bolt

0 Frank Livingston over 2 years ago in reply to Bolt Hsieh

TI__Mastermind 29388 points

Bolt,

Understood, we'll wait for your response.

Regards,
Frank

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LP-AM243: How to configure GPIO Event trigger for BCDMA operation