AM2432: Question regarding to get power-on-reset status due to power loss

Hong Zhang

Part Number: AM2432

Hello,

I am reading the spruim2d.pdf to try to find a register that could represent the status to tell when the board lost power and experienced a Power-on-reset due to power loss, but I didn't find one for the main domain register. From SDK, SOC_getWarmResetCauseMainDomain() this function could read the rst_src register from main domain, but it doesn't have a field to represent power-on-reset due to power loss.

Is there a register for r5f core to access on the main domain that could represent power-on-reset due to power loss?

Thanks,

Hong

over 2 years ago

0 Aakash Kedia over 2 years ago

TI__Mastermind 26145 points

Hi Hong Zhang,

Due to Public Holiday in US, please expect a delay in response.

Best Regards,
Aakash

0 Fleenor over 2 years ago

TI__Mastermind 22863 points

Hey Hong,

The TOPRCM_WARM_RST_CAUSE Register captures the source for both Warm and Power-On Resets. Full Power Tree/PORz reset implementations should be evaluated on a per-system basis. Sudden power loss should inevitably result in a PORz reset.

This is equivalent to:

12'b 0000_0100_0001 - POR reset (PORz)

https://ti.com/lit/pdf/spruj42

Best Regards,

Zackary Fleenor

0 Hong Zhang over 2 years ago in reply to Fleenor

Intellectual 782 points

Hello Zackary,

Thanks a lot for the information,

I checked the document you listed, which is called AM263x Register Addendum. Is the register Addendum same between AM243x and AM263x? Does ti have similar document for AM243x?

Thanks a lot,
Hong

0 Hong Zhang over 2 years ago in reply to Hong Zhang

Intellectual 782 points

Hello Zackary,

Thanks a lot for the information,

0x5320000c listed in https://ti.com/lit/pdf/spruj42 doesn't seem to be a valid address for AM2432, which caused abort whenever it tries to read from this address.

What is the register address for AM2432? Is there a document about it?

Thanks a lot,
Hong

0 Daniel Bermudez over 2 years ago in reply to Hong Zhang

TI__Expert 7540 points

Hi Hong,

I believe this is a slight confusion from our part so I apologize, we gave you the AM263x Register Addendum rather than the corresponding register for AM243x. Please try the following:

Download latest TRM for AM243x, spruim2d is an old version:
- AM64x /AM243x Processors Silicon Revision 2.0 Texas Instruments Families of Products (ti.com)
I believe the register Zackary was pointing you to in the AM263x addendum should correspond to this one in AM243x:

CTRLMMR_RST_SRC Register Captures the source for both Warm and Power-on Resets. In AM243x the two bitfields associated with these are bits 25 and 24:

Hope this helps!

Best,

Daniel

0 Hong Zhang over 2 years ago in reply to Daniel Bermudez

Intellectual 782 points

Hello Daniel,

I exercised this register, but after the board lost its power and came back from power-on-reset, this register CTRLMMR_RST_SRC always reads to 0.

Hong

0 Daniel Bermudez over 2 years ago in reply to Hong Zhang

TI__Expert 7540 points

Hi Hong,

This is because internal memory gets wiped during a power loss so you wouldn't be able to read the previous contents of the register. If that is the case then you could try to implement an ESM interrupt that triggers upon an under-voltage event. Details on this can be found in the following thread:

(+) MCU-PLUS-SDK-AM243X: SYS-MON UV Interrupt Event on R5F - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Please go through the thread and let me know if the provided example in it would be useful for your usecase

Best,

Daniel

+1 Fleenor over 2 years ago in reply to Hong Zhang

TI__Mastermind 22863 points

Hey Hong,

In additional to Daniel's response (where the user application would try to detect sudden power loss and perform a controlled PORz reset). It should be assumed that if CTRLMMR_RST_SRC is read as 0, that the last reset was due to a device-level PORz. This could be triggered by sudden power loss as mentioned, or by a state change of the MCU_PORz pin from any upstream failure in the power distribution network.

I hope this helps to provide additional clarity regarding device reset operations. Happy to answer and follow up questions.

Best Regards,

Zackary Fleenor

0 Hong Zhang over 2 years ago in reply to Fleenor

Intellectual 782 points

Hello Zackary,

Sorry about the late reply. I have leveraged the case when CTRLMMR_RST_SRC reads to be 0, last reset was due to a device-level PORz. Thanks a lot for confirming about this.

Thanks,

Hong