• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 193 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2431: The SPI timing question

Rajeev Bharol
Prodigy 90 points
Part Number: AM2431

Hi,
What I have noticed is that once the transmit FIFO is written into and the bytes are being sent over the bus, the time difference between any two bytes is about 190 nS. On TM4C it is 128nS. Why is that so? Can the firmware control this time between the bytes that are sent out?

Thanks
Rajeev Bharol

  • 0
    TI__Guru 55155 points

    Hi Rajeev,

    The delay between the two transmit frames is fixed by the McSPI IP. It is not controllable by the firmware.

    To increase the throughout. You may want to increase the frame size (8bit to 32bits).

    Best regards,

    Ming