AM2431: Question about the SPI read logic in SDK version 08.05

Hi, ex
I am looking at the example code from mcspi_performance_8bit_am243x-lp_r5fss0-0_freertos_ti-arm-clang example in latest version of SDK. In the example code, it waits for Tx FIFO to be empty before writing the bytes and similarly it waits for Rx FIFO to be full before reading any bytes out.

My question is, why does it have to wait for tx FIFO to be empty before writing the bytes in? Can it not write a byte as soon as TXS (bit 1 in status register) is 1 indicating the register is empty? Similarly during read can it not just wait for RXS bit to be 1 and read the byte as soon as it shows up? What difference would it make if we do it this way?

Here is the code from the example:

while (transferLengthTx != 0)
{
if (0 != (MCSPI_readChStatusReg(baseAddr, chNum) &
CSL_MCSPI_CH0STAT_TXFFE_MASK))
{
/* Write Effective TX FIFO depth */
if (transferLengthTx >= effTxFifoDepth)
{
transferLengthTx = effTxFifoDepth;
}
/* Write the data in Tx FIFO. */
for (i = 0; i < transferLengthTx; i++)
{
MCSPI_writeTxDataReg(baseAddr, (uint8_t) (*txBuff++), chNum);
}
numWordsWritten += transferLengthTx;
transferLengthTx = length - numWordsWritten;
}
if (0 != (MCSPI_readChStatusReg(baseAddr, chNum) &
CSL_MCSPI_CH0STAT_RXFFF_MASK))
{
/* Write Effective TX FIFO depth */
if (transferLengthRx >= effTxFifoDepth)
{
transferLengthRx = effTxFifoDepth;
}
/* Write the data in Tx FIFO. */
for (i = 0; i < transferLengthRx; i++)
{
*rxBuff++ = (uint8_t) MCSPI_readRxDataReg(baseAddr, chNum);
}
numWordsRead += transferLengthRx;
transferLengthRx = length - numWordsRead;
}
}



Thanks
Rajeev