[FAQ] AM2x: FreeRTOS Multiprocessing?

Alexander Baehr

Part Number: LP-AM243

Hi experts,

I am evaluating AM243x with MCU+SDK 8.5.0.24.

I noticed in the FreeRTOS docs that FreeRTOS has a multiprocessing feature called SMP, which would be an interesting option for AM243x.

Is this feature included in the TI FreeRTOS port? Is there an example how to set it up (i. e. what to start on which core)?

Best regards

Alexander

over 2 years ago

0 Aakash Kedia over 2 years ago

TI__Mastermind 26145 points

Hi Alexander Baehr,

SMP cannot be supported on R5 Pulsar System because the R5 CPUs do not have shared Cache Memories. I have assigned the ticket to the experts who can share more details on the same.

Best Regards,
Aakash

+1 Prasad Jondhale over 2 years ago in reply to Aakash Kedia

TI__Mastermind 27743 points

Hi Alexander,

As Aakash mentioned, due to lack of HW cache coherency support in AM2x R5F subsytems, we do not expect SMP implementation to yield reasonable performance across different use cases and not going to support this in SDK.

However, customers may evaluate their own and explore options like core affinity based optimizations depending on use case.

There are certain ways to achieve this as discussed in below thread. Please note that we don't have full details nor the plan to support it so customers needs to evaluate on their own.

https://forums.freertos.org/t/smp-porting-to-cortex-r5/14133/20

Regards

Arm-based microcontrollers

Arm-based microcontrollers forum

[FAQ] AM2x: FreeRTOS Multiprocessing?