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AM2432: ECC Aggregator Diagnostic Error Injection

Part Number: AM2432

Hello Support Team,

in our current project we want to use the AM2432 MCU with ECC memory. On the MCU_M4FSS we use the internal SRAM (256KB IMEM/DMEM with ECC). Now we want to test cyclically the ECC checker for diagnostic purpose. In chapter "12.6.4.3.6 Inject Only Mode" is written:

"There are modules that already perform the ECC generation and checking as part of their data path. In this case, the ECC wrapper may be configured in inject only mode, if needed. In this mode the ECC wrapper does not perform ECC detection and correction. The inject only mode allows users to inject single or double-bit errors so that the module logic can be tested for diagnostic purposes.

Note
There is no software control to enable inject only mode. It is configured via tie-off value. Inject only and ECC modes are mutually exclusive.

 The interconnect ECC component also supports error injection mode. There is error injection logic for testing of the error checking logic (checkers)."

Does this mean, the diagnostic error injection is not working with the internal SRAM?

In a later project we want to use one R5F core with the 2MB SRAM (with ECC) and DDR4 (with inline ECC). Is the diagnostic error injection working on these ECC wrappers?

Best Regards,

Stephan

  • Hi

    We are looking into this issue

    Regards

    Sri Vidya

  • Hi Stephan,

    The statement you are referring to in the above description essentially states that, the ECC Fault injection mode can be used to voluntarily inject single or double bit errors into the RAM area, once you inject the error, you can trigger the ECC module to perform a error detection and signal it to the CPU using the ESM signal handlers. As of now, we don't have any ECC SDL driver available.

    Hope this helps.

    Thanks,
    G Kowshik

  • Hi Kowshik,

    thank you for your answer.

    The ESM module is not mentioned in the ECC Aggregator chapter 12.6.4 of the TRM. My understanding is, that I can trigger a fault injection by writing into the registers ECC_CBASS_ERR_CTRL1 and ECC_CBASS_ERR_CTRL2 like described in chapter "12.6.4.3.6 Inject Only Mode". Following this procedure, this will force an ECC error, which is signaled by the ECC wrapper. The event is visible in the ECC status and error registers. Optionally I configure an interrupt for this.
    Is this correct?

    This procedure is working on the ECC wrapper for the internal SRAM (256KB IMEM/DMEM with ECC) and for the 2MB SRAM (with ECC) and DDR4 (with inline ECC) in the same way.
    Is this correct?

    According to the description above
    "... the ECC wrapper may be configured in inject only mode, if needed. In this mode the ECC wrapper does not perform ECC detection and correction. "
    Does this mean, if I want to test the ECC logic of the CPU
     1. I have to re-configure the ECC wrapper to "Inject Only Mode".
     2. I do the fault injection like described above.
     3. I handle the error detection and correction result.
     4. I re-configure the ECC wrapper back to ECC correction.
    Is this correct?

    Best Regards,
    Stephan

  • Hi Stephan,

    Is this correct?

    Your understanding is slightly flawed here. Please note that, the ECC wrapper around a particular memory area will always be working and guarding the memory looking for the errors.

    If there is any single bit errors - > It can detect them and also Correct them.

    If there are any double bit errors -> It can only detect them and signal them through the ESM to CPU via ESM interrupts. It CANNOT correct them.

    So, in your steps, just enabling the inject mode should be fine to test the diagnostic feature. This is the data I have received from the experts internally.

    Thanks,
    G Kowshik