• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 30 subscribers
  • Views 248 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LC4357: Ethernet Rx Interrupt Failing to Trigger

Thomas Hickey
Prodigy 70 points
Part Number: TMS570LC4357

Hi,

I am currently trying to get ethernet communications to work between our TMS570 & a DP83822HFRHBR in a baremetal environment for a bootloader. As it currently stands communications seem to work from anywhere between 2-10 minutes before cutting out and failing beyond that point. I have based my project off of the following example project published by TI: https://git.ti.com/cgit/hercules_examples/hercules_examples/tree/Application/LwIP?h=master

I follow the same process for initializing the EMAC/MDIO modules and for receiving ethernet data as is done in the example above. I also have the same code functioning fine without the TCP server failing in a FreeRTOS environment with the only difference being that the processing of the ethernet packet is done in a task as opposed to in the interrupt itself.

I am seeing the following behavior:

  1. C0_RX_PULSE interrupt behaving fine up until a random point
  2. C0_RX_PULSE interrupt no longer being triggered

This is a logic analyzer capture of the behavior I am seeing. Relevant signals are "EthRxInt" & "3v3". "EthRxInt" refers to GPIO pins I have set within the C0_RX_PULSE interrupt upon entrance & exit. The "3v3" line is the power rail being supplied to the DP83822HFRHBR and is stable.

In order to test the stability of the TCP server that I am running on the TMS570 I am simply sending out pings to the device & seeing if the server responds to the ping. These pings trigger the C0_RX_PULSE interrupt & processing of the pings is carried out in the interrupt. Upon failing these are the states of relevant EMAC/MDIO registers:

RXINTMASKS:

RXUNICASTSET / RXMBPENABLE:

RXUNICASTCLEAR:

C0RXEN:

Interrupt Flag:

MDIO CLK @ 1 MHz:

If you have any input as to why I would be seeing this behavior or if you need me to provide you with any more information in regards to the code I am running or register status upon failure please let me know. I appreciate any help you are able to provide.

Thanks,

Thomas Hickey