Hello,
Our boards include a '245 buffer that drives the user's boot mode selection onto the SOP pins around PORz. This buffer is tristated after the SOP pins sensing. In my understanding, this is to avoid loading the corresponding SPI and QSPI pins, which would affect the timings (rise and fall times) during normal operation after PORz. Is this correct?
The concern is that this increases the bill of materials. Customers may want to avoid this buffer and just have the pull resistors on the SOP lines. Do we have simulation data or guidelines to help customers achieving the maximum QSPI operating frequency while avoiding such a buffer?
Best regards,
François.