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MSPM0G3507: I2C interrupts question from customer

Wolfgang Wendler TI
Intellectual 2310 points
Part Number: MSPM0G3507
Other Parts Discussed in Thread: SYSCONFIG

Hi MSPM0 team,

Asking on behalf of a customer who has issues with I2C (configured as slave) interrupt functionality in the latest SDK. They need support for the function DL_I2C_enableTargetTXEmptyOnTXRequest()  would enable TX fifo empty interrupt to be triggered only when a read request is made by the I2C host.

As of now, the TX fifo empty interrupt is triggered immediately when the MCU starts up, since the fifo is empty, and the interrupt driver cannot determine whether it was triggered by a host data read request or just en empty fifo.

Do you have an estimated date for function DL_I2C_enableTargetTXEmptyOnTXRequest()  to be available in a future SDK release?

Thanks,

/ Wolfgang

  • 0
    TI__Genius 9820 points

    Hi Wolfgang,

    I will check the issue later.

    Thanks,

    Yuhao

  • 0
    Prodigy 20 points

    I (the customer) downloaded the latest CSS Theia 1.0.0 and SDV version mspm0_sdk_1_00_00_04. Using sysconfig I can now select "Enable Target TX Empty Interrupt" causing function DL_I2C_enableTargetTXEmptyOnTXRequest() to be called by the generated source code.

    When I flash/start the MCU, the interrupt DL_I2C_IIDX_TARGET_TXFIFO_EMPTY is called even though no I2C traffic has been sent to the I2C slave. I thought the purpose of DL_I2C_enableTargetTXEmptyOnTXRequest() was that the interrupt DL_I2C_IIDX_TARGET_TXFIFO_EMPTY shall be called then a I2C master requests/reads data. I.e. when DL_I2C_IIDX_TARGET_TXFIFO_EMPTY is called the I2C client can place data in the queue using e.g. DL_I2C_fillTargetTXFIFO().

    The reason for this question is that I need do know when the I2C master wants to read data. Other MCUs (e.g. some ST models) has a callback that is called upon a matching I2C address, and that callback shows the value of the read/write bit.

    The I2C protocol for reading data looks likt this (for reading 4 bytes):
    * 1byte  1byte      1byte                    1byte    1byte    1byte    1byte
    * +-----+--------+-+-----+-+-----+--------+-+------+-+------+-+------+-+------+-+----+
    * |START| Addr+W |A| Reg |A|START| Addr+R |A| Val3 |A| Val2 |A| Val1 |A| Val0 |N|STOP|
    * +-----+--------+-+-----+-+-----+--------+-+------+-+------+-+------+-+------+-+----+

    This is the answer I received earlier in an email conversation with Ti support:
    On PG2, there will be the option to enable a "transmit request" interrupt on the target (via DL_I2C_enableTargetTXEmptyOnTXRequest) which will only fire "TX fifo empty" interrupt when there is a incoming request for data.