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TMS570LC4357: EPC captures CPU-detected correctable ECC errors even when CPU event bus is disabled

Andy
Prodigy 20 points
Part Number: TMS570LC4357

TMS570LC4357 TRM (SPNU563A) section 2.2.3.2 says that both single- and double-bit ECC errors are indicated to the EPC via the CPU event bus:

This is also indicated by Table 2-4 and section 4.3.2.

However, in an experiment where I intentionally scan over erased flash memory (which I know looks full of both correctable and uncorrectable ECC errors) with 64-bit CPU reads, I see correctable error EPC CAM entries appear for erased flash addresses I am reading, even though the CPU event bus is disabled in the Cortex-R5 PMU. Once the scan gets far enough that the CAM fills, I can also see FIFOFULLSTAT.FULL0 and OVRFLWSTAT.OVFL0 become set, which confirms the errors are coming from the CPU and not some other bus master.

PMCR.X is cleared at this point (CPU event bus is off):

I do not see any ESM 2.3 events when I scan over erased flash words that read as uncorrectable ECC errors, so at least that response is still disabled when the CPU event bus is disabled.

My question is: How is it possible the EPC is receiving these correctable error events from the CPU, if the event bus is disabled at the time?

Is it possible that correctable errors from the CPU are actually not indicated to the EPC with the CPU event bus, but with a separate mechanism?

Thank you!

  • 0
    TI__Guru**** 192326 points

    Hi Andy,

    To test 1-bit or 2-bit ECC error, please use the flash API of Safety Diagnostic Library:

    retVal = SelfTest_Flash(FLASH_ECC_TEST_MODE_1BIT, TRUE, &failInfoFlash);
    retVal = SelfTest_Flash(FLASH_ECC_TEST_MODE_2BIT, TRUE, &failInfoFlash);

    The EPC captures the addresses of ECC errors into a 16-entry CAM. If the error address is already in the CAM, the error is discarded, and no ESM flag is set. If the address is not in the CAM, and the CAM has empty entries, the address is added into the CAM, and ESM flag is set. if the address is not in the CAM list, and the CAM has no empty entries, always raise a signal to the ESM.

  • 0 in reply to QJ Wang
    Prodigy 20 points

    Hello QJ, thank you for the reference.

    The internal CAM workings of the EPC make sense. However, I am still confused about how in my situation the EPC registered the CPU-detected ECC errors while the CPU event bus was still disabled. This seems impossible if the CPU event bus is what reports them to the EPC?

    Thank you again for the assistance!

  • +1 in reply to Andy
    TI__Guru**** 192326 points

    Hi Andy,

    You are correct. I noticed this issue on LC43x. It might be a bug in ARM Cortex-R5 CPU.

  • 0 in reply to QJ Wang
    Prodigy 20 points

    Thank you!