TMS570LC4357: Explanation of registers

LayEng Chan

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

I am developing codes for tmp570LC4357 for the first time. I have been reading TMS570LC43x 16-32 RISC Flash Microcontroller Technical Reference Manual (Rev. A) a lot as I develop. I am studying n2het. There seems to be missing specs definitions. To start off, I don't find details of HETINTENAS , HETOFF1, HETOFF2. Eg for HETINTENAS. The explanations provided is

Interrupt Enable Set bits. HETINTENAS is readable and writable in any operation mode.Writing a 1 to bit x enables the interrupts of the N2HET instructions at N2HET addresses x+0, x+32, x+64, and so on. Generating an interrupt requires to set bit x in HETINTENAS and to enable the interrupt bit in one of the instructions at addresses x+0, x+32, x+64, and so on. To avoid ambiguity, only one of the instructions x+0, x+32, x+64, and so on, should have the interrupt enable bit (inside the instruction) set. Writing a 0 to HETINTENAS has no effect.When reading from HETINTENAS bit x gives the information, if N2HET instructions x+0, x+32, x+64, and so on, have the interrupt enabled or disabled

But which bit is pwm, edge interrupts . It gets auto generated by halcogen. I can't cross check the code generated with the specs definitions. Is it possible for you to give an example of pwm1 and edge 2 interrupts and explain how to set and read back these registers?

Thanks for your support.

over 3 years ago

0 jagadish gundavarapu over 3 years ago

TI__Guru* 77936 points

Hi LayEng,

On one of my recent threads, i created a edge interrupt on HET1 pin.

Can you please check whether that would be helpful to understand how to generate edge and PWM interrupts?

(+) TMS570LS1227: The HET is used as a GIO input to trigger a falling edge interrupt - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Thanks & regards,
Jagadish.

0 LayEng Chan over 3 years ago in reply to jagadish gundavarapu

Prodigy 210 points

Dear Jagadish

Thank you for your reply. It would be helpful if you can give me the the hcg file to your solution as it is more graphic. I would like to see the pwm interrupts. I also want to ask about some definitions: High level level interrupts is refering to high priority interrupt and low level interrupt is normal priority. If high level interrupt is high priority, then why is there still a choice for fiq and irq in vim channel for the high level interrupt? Is high level interrupt = fiq? Looking forward to your reply. Thank you.

0 jagadish gundavarapu over 3 years ago in reply to LayEng Chan

TI__Guru* 77936 points

Hi LayEng,

LayEng Chan said:
It would be helpful if you can give me the the hcg file to your solution as it is more graphic.

I didn't generate any code from HET IDE for edge trigger interrupt purpose. All the required configurations for shared project were performed in HALCoGen GUI only.

LayEng Chan said:
High level level interrupts is refering to high priority interrupt and low level interrupt is normal priority. If high level interrupt is high priority, then why is there still a choice for fiq and irq in vim channel for the high level interrupt? Is high level interrupt = fiq? Looking forward to your reply.

These high priority and low priority configurations are meant for N2HET peripheral only. That means this configuration of high- and low-level priority will applicable for all the edge and PWM interrupts that are available in N2HET only.

But this FIQ and IRQ configuration is at processor level, there could be other interrupts also possible along with N2HET interrupts right like CAN, SCI and SPI etc. all these interrupts can be configured in either FIQ or IRQ.

Thanks & regards,
Jagadish.