Hi,
I'm working with the Hercules RM46 dev board and intend to use the TMS570 on our custom board.
I'm focusing on the EMAC driver right now and I'm wondering something.
In the TRM it is written (31.2.17.1.1): "the EMAC issues an interrupt to the CPU when it writes the packet’s last buffer descriptor address to the appropriate channel queue’s transmit completion pointer located in the state RAM block"
But is the completion pointer also updated in the case transmission was abandoned because of collision or carrier sense error (or other if I missed them).
If it's the case, it's okay.
However, if it's not, that might mean that the tail of BD is never reached (in case error occurs for that tail) and that I have no way to provide new packets/BDs to the EMAC again.
Could you clarify it please?
Since I'm talking about errors, I also wanted to be sure that I understood it well:
Errors can be checked only through STAT registers/interrupts. And it’s not clear when STAT is updated. I conclude it is simply not meant to be used for error checking.
Could you confirm that I'm right?
Thanks in advance,
Laurent