Hi,
In TMS570LS31x/21x Microcontroller Silicon Revision C Errata, there is a design exception titled CORTEX-R4#57.
The condition specified in the errata document for this to happen is:
The issue requires the following sequence of instructions in ARM state:
1. - VMRS APSR_nzcv, FPSCR (formerly FMSTAT), where the condition on the instruction is not always.
This instruction immediately following:
2. A flag-setting integer multiply or multiply and accumulate instruction (e.g. MULS)
3. A single-precision floating-point multiply-accumulate (FP-MAC) instruction (e.g. VMLA), timed such that the accumulate operation is inserted into the pipeline in the cycle in which the VMRS instruction is first attempted to be issued.
To meet the above timing requirements, the VMRS instruction must be three pipeline stages behind the FPMAC. Depending on the rate in which the instructions are fetched, interlocks within this sequence and dual-issuing, this can be up to three other instructions between this pair.
Following is the query:
1. Is the sequence of instructions as indicated below. The highlighted area is confusing.
- MULS
- VMRS APSR_nzcv, FPSCR
- VMLA
2. What would be a sample code snippet in high level language that would result in this sequence of assembly instructions?
Thanks
Nisha
