TM4C1294NCPDT: TI board I2C high speed issue

Hi,

  Did you set up the slave for high speed operation with HS bit equal to 1 for the speed to receive the master code byte? 

  Can you show your logic analyzer capture?

  Can you also look go through this app note particularly section 5.4 about high speed operation? https://www.ti.com/lit/pdf/spma073

Hi CHarles,

Thanks for your reply. Actually TI I2C master performance no issue. Yesterday I tried to decrease the I2C speed from 3Mhz to 2.7Mhz, the same fw project and TI board_Slave role start to work. I think TI board_I2C slave cannot achieve over 3Mhz speed. Pls kindly advise.

Best Regards

Hongwei 

Hi Charles,

If TI I2C as slave role, aft master side sending master code followed by slave address with 3.1Mhz speed, TI board gave NACK. But if master side decreased high speed from 3.1Mhz to 2.7Mhz, TI_Slave communication worked fine and run overnight no issue. 

Best Regards

Hongwei 

Hi Hongwei,

  Not really sure what is the cause of the problem. Are you meeting the I2C electrical characteristic requirements for I4 and I10 parameters  shown in the datasheet. See below table. What is the your system clock speed? What pullup resistor do you use? For high speed operation, I would have expected a stronger pullup (lower resistance value) compared to the stand speed for 100kHz. Does it make a difference if you change the pullup resistors?

Hi Charles,

I noticed the pull up resistor already and so far the pull up resistor value is about 200 ohm for I2C spec request. and TI_Slave CLK config shown above. Actually strange is TI_I2C_Master_3.4Mhz no issue, however when it works as slave which cannot achieve 3Mhz or over. For data hold time let me check it later but I don't think something problem of data hold time as master side board match the I2C spec already. And one more thing I found when TI_I2C working with high speed mode, fw has to add delay to make sure high speed mode working properly.

Best Regards

Hongwei 

Hi Hongwei,

  I feel it has something to do with the timing (e.g. setup or hold time).  As you indicated, it will work at around 3Mhz but not 3.4Mhz.  Did the slave capture wrong data in its FIFO or simply not capturing anything? 

  Can you do one experiment? Instead of running system clock at 120Mhz, can you try a lower speed. Maybe start with 25Mhz using OSC as the source clock instead of using PLL. I just wanted to know if there is any relationship between the system clock speed and your observation. 

Hi Charles,

Sure, let me debug it later and update you, thanks so much.

Best Regards

Hongwei

Hi CHarles,

Sure, thanks.

Best Regards

Hongwei