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RM46L852: Booting Main application from CAN Bootloader results in prefetchEntry System Interrupt

Dana Rich
Prodigy 10 points
Part Number: RM46L852
Other Parts Discussed in Thread: UNIFLASH, HALCOGEN

I'm working on implementing a bootloader to update an RM46 over CAN. I've based my project the example CAN bootloader provided by TI and have been reasonably successful. I'm at the stage now where having successfully written the received image to flash, I'm attempting to boot into the image. However, when I do this, I get caught in a prefetch system interrupt (address 0x1002C).

Some background information:

  • ECC (ram) is enabled for the bootloader, however I currently have it disabled (ram & flash) for the main application.
  • The Main application is an existing application that works when programed with CCS
    • I do not have Auto ECC Generation enabled in CCS
    • I erase the necessary sectors only (for Program Load)
  • I cannot boot the main application when I load the bootloader and the main application through Uniflash (boot to app is forced)
  • I have adjusted the linker file for the main application to direct to what I believe are the correct locations.
  • I have sys_intvecs.asm of the bootloader redirecting to the location of the vector for the main application in flash.

Below you'll find copies of both linker files, and attached, the HALCoGen project files.

Main App Linker cmd file:

/*----------------------------------------------------------------------------*/
/* sys_link.cmd                                                               */
/*                                                                            */
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

/*                                                                            */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN (0) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */

--retain="*(.intvecs)"

/* USER CODE BEGIN (1) */
/* IGNORE the generated Memory code, overridden below */
#if 0
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */

MEMORY
{
    VECTORS (X)  : origin=0x00000000 length=0x00000020
    FLASH0  (RX) : origin=0x00000020 length=0x0013FFE0
    STACKS  (RW) : origin=0x08000000 length=0x00005800
    RAM     (RW) : origin=0x08005800 length=0x0002a800

/* USER CODE BEGIN (2) */
#endif
/* Override Memory Segments with CRC here */
#if 1
MEMORY
{
    VECTORS (X)  : origin=0x00010020
                   length=0x00000020
                   vfill = 0xffffffff

    CRCMEM  (RX) : origin=end(VECTORS)
                   length=0x000001E0
                   vfill = 0xffffffff

    FLASH0  (RX) : origin=end(CRCMEM)
                   length=(0x0013FFFF - end(CRCMEM))
                   vfill = 0xffffffff

    STACKS  (RW) : origin=0x08000000
                   length=0x00004c00

    RAM     (RW) : origin=0x08004c00
                   length=0x0002b400
#endif
#if 1
    ECC_VEC  (R) : origin=(0xf0400000 + (start(VECTORS) >> 3))
                   length=(size(VECTORS) >> 3)
                   ECC={algorithm=algoL2R4F021, input_range=VECTORS}

    ECC_CRC  (R) : origin=(0xf0400000 + (start(CRCMEM)  >> 3))
                   length=(size(CRCMEM)  >> 3)
                   ECC={algorithm=algoL2R4F021, input_range=CRCMEM }

    ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0)  >> 3))
                   length=(size(FLASH0)  >> 3)
                   ECC={algorithm=algoL2R4F021, input_range=FLASH0 }
#endif
/* USER CODE END */
}

/* USER CODE BEGIN (3) */
/* IGNORE the generated Sections code, overridden below */
ECC
{
    algoL2R4F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
                   hamming_mask = R4         /* Use R4/R5 build in Mask */
                   parity_mask  = 0x0c       /* Set which ECC bits are Even and Odd parity */
                   mirroring    = F021       /* RM57Lx and TMS570LCx are build in F021 */
}
#if 0
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
    .intvecs : {} > VECTORS
    .text    : {} > FLASH0
    .const   : {} > FLASH0
    .cinit   : {} > FLASH0
    .pinit   : {} > FLASH0
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM


/* USER CODE BEGIN (4) */
#endif
/* Override Sections with CRCs here */
#if 1
SECTIONS
{
    .intvecs : {} > VECTORS, crc_table( _crc_table, algorithm=CRC32_C )
    .text  align(32) : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C )
    .const align(32) : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C )
    .cinit align(32) : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C )
    .pinit align(32) : {} > FLASH0
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM

    .TI.crctab : {} > CRCMEM
#endif
/* USER CODE END */
}

/* USER CODE BEGIN (5) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Misc                                                                       */

/* USER CODE BEGIN (6) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/

Bootloader Linker Cmd File:

/* Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/*                                                                            */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN (0) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */

--retain="*(.intvecs)"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */

MEMORY
{
/* Bank 0 (384kB) */
    VECTORS (X)  : origin=0x00000000
                   length=0x00000020
                   vfill = 0xFFFFFFFF

    FLASH0  (RX) : origin=end(VECTORS)
                   length=(0x00140000 - size(VECTORS))
                   vfill = 0xFFFFFFFF

    SRAM    (RW) : origin=0x08002000
                   length=0x0002D000

    STACKS  (RW) : origin=0x08000000
                   length=0x00002000

/* USER CODE BEGIN (2) */
#if 1
/* Bank 0 ECC */
    ECC_VEC  (R) : origin=(0xf0400000 + (start(VECTORS) >> 3))
                   length=(size(VECTORS) >> 3)
                   ECC={algorithm=algoL2R4F021, input_range=VECTORS}

    ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0)  >> 3))
                   length=(size(FLASH0)  >> 3)
                   ECC={algorithm=algoL2R4F021, input_range=FLASH0 }

#endif
/* USER CODE END */
}

/* USER CODE BEGIN (3) */
ECC
{
    algoL2R4F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
                   hamming_mask = R4         /* Use R4/R5 build in Mask */
                   parity_mask  = 0x0c       /* Set which ECC bits are Even and Odd parity */
                   mirroring    = F021       /* RM57Lx and TMS570LCx are build in F021 */
}
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */


SECTIONS
{
   .intvecs : {} > VECTORS

   flashAPI:
   {
     ./Fapi_UserDefinedFunctions.obj (.text)
     ./bl_flash.obj (.text)
     --library= "/home/fw/fwbl/flashAPI/F021_API_CortexR4_LE.lib" (.text)
   } palign=8 load = FLASH0, run = SRAM, LOAD_START(apiLoadStart), RUN_START(apiRunStart), SIZE(apiLoadSize)

   .text  : {} > FLASH0 /*Initialized executable code and constants*/
   .const : {} palign=8 load=FLASH0, run = SRAM, LOAD_START(constLoadStart), RUN_START(constRunStart), SIZE(constLoadSize)

   .cinit : {} > FLASH0 /*Initialized global and static variables*/
   .pinit : {} > FLASH0
   .data  : {} > SRAM
   .bss   : {} > SRAM   /*Uninitialized Global and static variables */
   .sysmem  : {} > SRAM

/* USER CODE BEGIN (4) */
/* USER CODE END */
}

/* USER CODE BEGIN (5) */
/* USER CODE END */

Bootloader HCG.zip

APP HCG.zip

Bootloader sys_intvecs.asm

;-------------------------------------------------------------------------------
; sys_intvecs.asm
;
; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
;
;
;  Redistribution and use in source and binary forms, with or without
;  modification, are permitted provided that the following conditions
;  are met:
;
;    Redistributions of source code must retain the above copyright
;    notice, this list of conditions and the following disclaimer.
;
;    Redistributions in binary form must reproduce the above copyright
;    notice, this list of conditions and the following disclaimer in the
;    documentation and/or other materials provided with the
;    distribution.
;
;    Neither the name of Texas Instruments Incorporated nor the names of
;    its contributors may be used to endorse or promote products derived
;    from this software without specific prior written permission.
;
;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;
;

    .sect ".intvecs"
    .arm

;-------------------------------------------------------------------------------
; import reference for interrupt routines

    .ref _c_int00

;-------------------------------------------------------------------------------
; interrupt vectors
; Please change the #0x???? for your specified image location defined in bl_config.h - 0x08

        b   _c_int00   ;0x00
        b   #0x10018   ;0x04 UNDEF; 0x10000-0x08
        b   #0x10018   ;0x08 SVC  ; 0x10000-0x08
        b   #0x10018   ;0x0C PABT ; 0x10000-0x08
        b   #0x10018   ;0x10 DABT ; 0x10000-0x08

reservedEntry
        b   reservedEntry      ;0x14, reserved
        b   #0x10018           ;0x18, irqDispatcher
        ldr pc,[pc, #-0x1b0]   ;0x1C, FIQ


;-------------------------------------------------------------------------------

  • 0
    Prodigy 10 points

    As an additional comment, when I enable Flash ECC in HalCoGen for the bootloader, I get UNDEF interrupt when executing the Fapi_BlockErase command. This does not occur when Flash ECC is disabled. I did modify the LCF to include flash bank 7 when doing this.

  • 0 in reply to Dana Rich
    TI__Guru 69811 points

    Hi Dana Rich,

    Started working on your issue and will provide an update soon.

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 10 points

    Thank You.

    I have a couple additional observations that may lead somewhere:

    • If I jump to the main application from the bootloader prior to executing anything from within _c_int00, we appear to load the application fine. 
    • If I make the HAL of the bootloader match the HAL of the application (minus interrupts), we appear to be able to load the application from the bootloader even after executing the bootloader's _c_int00.
    • When I look at the abort registers I see C3C3C3C6, which appears like PBIST test values.
    • I reconfigured the stacks in HCG, rather than using the linker file, to be identical between the bootloader and main application. This did not resolve anything.

    My thought right now is: does the processor need to be in supervisor mode prior to the jump to the main application? That's one obvious difference from executing _c_int00 from reboot vs jumping there from executing code.

  • 0 in reply to Dana Rich
    TI__Guru 69811 points

    Hi Dana,

    The attached zip files have only HALCoGen configuration files

    can i get your full application project folder?

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 10 points

    Unfortunately I'm uncomfortable providing the full project in this setting, however if there are specific files or functions you're looking for I think I could do that. I could also provide the HALCOGEN generated files too (including the changes we've made in the user sections).

  • 0 in reply to Dana Rich
    TI__Guru 69811 points

    Hi Dana,

    Is your application involving any FreeRTOS or it is just a bare-metal code?

    If it doesn't involve FreeRTOS, did you test with any basic LED blink project as application before using actual application?

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 10 points

    It's a bare-metal application. When I first kicked-off this endeavor, I leveraged a RM46 launchpad and tested the example bootloader and a demo-blink application, however that was very limited in scope and not on representative hardware or with representative firmware.

  • 0 in reply to Dana Rich
    TI__Guru 69811 points

    Hi Dana,

    Okay let me try CAN bootloader with some dummy application at my end first. I will share my suggestions after doing testing at my end once.

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    TI__Guru 69811 points

    Hi Dana,

    Apologies for the delay, we got consecutive leaves in TI India.

    I got free time today to test and provide updates.

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 10 points

    Thank you, any help would be greatly appreciated.

  • 0
    TI__Guru**** 196306 points
    Dana Rich said:
    he Main application is an existing application that works when programed with CCS

    Do you mean that both bootloader and Application are programmed through CCS? and both of them work?

    Dana Rich said:
    I cannot boot the main application when I load the bootloader and the main application through Uniflash (boot to app is forced)

    If you use bootloader to load the application, the ECC of the application can be calculated and programmed using Flash API.

    Have you checked that the application is programmed correctly starting at 0x10020?

  • 0 in reply to QJ Wang
    Prodigy 10 points
    QJ Wang said:
    Do you mean that both bootloader and Application are programmed through CCS? and both of them work?

    I mean that when using CCS, I can execute and step through the bootloader programmed at 0x00000. And in a separate operation, load and execute the main application programmed at 0x10020.

    QJ Wang said:
    If you use bootloader to load the application, the ECC of the application can be calculated and programmed using Flash API.

    With ECC (Ram and FLASH) disabled in the HAL, I am able to program and run the application through the bootloader. Inspecting the memory at the correct addresses and everything appears okay.

    If I want to use ECC in the application, do I need to enable ECC in the bootloader's HAL? 

    Am I able to use Uniflash to program both images with ECC enabled? Are there specific settings I need to do to accomplish this?

    Thanks,

    Dana

  • 0 in reply to Dana Rich
    TI__Guru**** 196306 points
    Dana Rich said:
    If I want to use ECC in the application, do I need to enable ECC in the bootloader's HAL? 

    yes, the ECC should be enable in bootloader and application.

    Dana Rich said:
    Am I able to use Uniflash to program both images with ECC enabled? Are there specific settings I need to do to accomplish this?

    Yes, it can program the both images separately.

    If you want to generate ECC using Linker CMD script, the "Auto ECC Generation" should be disabled when loading the *.out file.

    1. load bootloader with "Auto ECC Generation" enabled, and "Necessary Sectors only"

     

    2. then load Application with the same settings.

    3. The application starts from 0x10020 (VECTORS), so the destination address of the branch instruction in bootloader should be 0x10020:

    g_ulTransferAddress = (uint32_t)0x10020;
    ((void (*)(void))g_ulTransferAddress)();

    or

    ((void (*)(void))0x10020)();

  • 0 in reply to QJ Wang
    Prodigy 10 points

    Okay, thank you, that is consistent with how I have it set up. When I attempt to enable ECC in the bootloader, I encounter an abort when attempting to jump to  the _errata_CORTEXR4_66_() function.

    I did do some reconfiguration and set the start of vectors to 0x10000, but I can't imagine that's a problem. I did away with storage of the boot flag and all that in my implementation.

  • 0 in reply to QJ Wang
    Prodigy 10 points

    Sorry, I just want to clarify, 

    QJ Wang said:
    1. load bootloader with "Auto ECC Generation" enabled, and "Necessary Sectors only"

    This should be disabled correct?

  • 0 in reply to Dana Rich
    TI__Guru**** 196306 points

    Yes, Because you use the Linker CMD to generate ECC, the "Auto ECC Generation" should be disabled.

  • 0 in reply to QJ Wang
    Prodigy 10 points

    I have another question:

    I found that I needed to add the line 

    b   #0xFFF8            ;0x18 irqDispatcher
     to the sys.intvecs.asm file of the bootloader to support the main application. However I'd also like to incorporate the SCI DMA example project (spna213) into the code to allow for me to update an FPGA from the bootloader as well. I'm not sure how I would configure the interrupts so everything would work correctly.

  • 0 in reply to Dana Rich
    Prodigy 10 points

    Just following up on my last message. By leveraging FIQ interrupts I was able to incorporate the above project after making some small changes. However it was ultimately unnecessary as doing it with polling was sufficient.

  • 0 in reply to Dana Rich
    TI__Guru**** 196306 points
    Dana Rich said:

    I found that I needed to add the line 

    Fullscreen
    1
    b #0xFFF8 ;0x18 irqDispatcher
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     to the sys.intvecs.asm file of the bootloader to support the main application.

    You don't need to change this line. The destination location of ldr pc,[pc,#-0x1b0] is always pointing to VIM IRQ vector register. 

  • 0 in reply to QJ Wang
    Prodigy 10 points

    We're using the IRQ dispatcher, if I don't add that line, I get an error when running the application. I don't remember exactly which error, but some sort of abort.

  • 0 in reply to Dana Rich
    TI__Guru**** 196306 points

    Hi,

    The RM46x and TMS570 devices support three different interrupt modes:

    1. Index interrupt mode:  After the interrupt is received by the CPU, the CPU branches to 0x18 (IRQ) or 0x1C (FIQ) to execute the main ISR. The main ISR routine reads the offset register (IRQINDEX, FIQINDEX) to determine the source of the interrupt.

        I think you use this mode.

    2. Register vectored interrupts: Before enabling interrupts, the application has to initiate the interrupt vector table. After CPU receives an interrupt, it executes the instruction placed at 0x18 or 0x1C ( ldr pc,[pc,#-0x1b0] ) to load the address of ISR (interrupt vector) from the interrupt vector register.

    3. Hardware vectored interrupts: When CPU receives an interrupt, CPU reads the address of ISR directly from the VIC port instead of branching to 0x18. This mode is recommended, and the VIC is enabled in HAL generated startup code.