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AM2634: AM263x-CC Too big counter increment when debugging RTI peripheral with CCS

Filippo Bordon
Prodigy 40 points
Part Number: AM2634

When debugging with CCS the Timer (RTI) peripherals:

  • I double checked that RTIn_RTIGCTRL->COS is set to 0.
  • I double checked that CCS->Preferences->Run/Debug->View Performance->Minimum interval between steps is set to 0ms
  • I double checked that CCS->Debug Configurations->"debug configuration in use"->Target->Program/Memory Load Options->Disable interrupts->"when assembly stepping" is set.


Let's say I have a for loop that reads the RTIn_RTIFRC0 register. If I let the code run without debugging and I collect the data, I get meaningful values (i.e. about one step increment of the free running counter for each loop iteration, that somehow makes sense as the timer is running with 25MHz clock and RTIn_RTIUC0 increments every 40ns and compares with RTIn_RTICPUC0 that is set to 25, resulting in 1us increment of RTIn_RTIFRC0).

When stepping the code (even from disassembly window) I get that the RTIn_RTIFRC0 as incremented of about 200 ms between consecutive reads of the register, while I would expect the same behavior of when reading the RTIn_RTIFRC0 and not debugging it.

What is the reason for this ?

  • +1
    TI__Genius 15435 points

    Hi Filippo,

    This is a expected behaviour, because when you free-run the core, the timer increments normally, however your expectation might be that during the debug the timer peripheral halts when the core pauses, this is not true because the Halt EN bit is not SET. Which means the timer still continues to operate in the Free running mode even when the core is paused. To make the observations you expect, please write 0x1 to enable the following register 0x50D00454, TRM also have this information

    Thanks,
    G Kowshik

  • 0 in reply to Kowshik Gudimetla
    Prodigy 40 points

    Hi, thank you for the answer.

    Yes setting that register as you say it solves the issue I was facing. 

    For reference here is some code that would set the HALTEN of RTI0 i.e. if the Core R5A0 is used:

    #include <drivers/hw_include/soc_config.h>
    HW_WR_FIELD32(CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_RTI0_HALTEN, CSL_MSS_CTRL_RTI0_HALTEN_CR5A0_HALTEN, 1);
  • 0 in reply to Filippo Bordon
    TI__Genius 15435 points

    Hi,

    Glad that the issue is resolved, moving the thread to closed.

    Thanks