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MSPM0L1306: adc conversion time

Anjli Behl
Prodigy 715 points
Part Number: MSPM0L1306

HI,

 

What can I do to speed up the A/D Conversion time?

  • 0
    TI__Mastermind 28070 points

    Hi Anjli,

    What sample rate are you targeting? Take a look at the adc12_max_freq_dma_LP_MSPM0L1306 example in the SDK. This example configure the MSPM0L for the maximum sampling rate. 

    Things like your conversion resolution, sample time settings, and trigger source can determine your overall sample rate.

    Best Regards,
    Brandon Fisher

  • 0 in reply to Brandon Fisher94
    TI__Genius 10620 points

    For this response, I'm referencing both the device datasheet and Technical Reference Manual (TRM).

    There are three components that will drive the total conversion time.

    1. Trigger minimum width
    2. Sample Time required to charge the internal ADC capacitance
    3. Conversion Time

    The TRM has a diagram of this sequence in section 9.2.9.1.

    Trigger

    Has a minimum of 3 ADCCLK cycles for software trigger. For hardware trigger sources, this will be 2 or 3 ADCCLK cycles.

    Sample Time

    You can see from table in the datasheet section 7.12.2 different proposed sampling times under different source conditions to the ADC. Essentially what matters is the external drive strength capability into the ADC, and this is design dependent. If you know your source characteristics, you can calculate the sample time you need based on the datasheet section 7.12.1 specification of a 4pF sample-and-hold cap with 0.5k ohm series resistance. You also need to account for the pin capacitance (CI). This is basic RC time constant math. The datasheet section 7.12.4 has a nice diagram of the internal circuitry of ADC to help you visualize this.

    The sample period is adjusted by the SAMPCLK bits of the ADC CLKCFG register, as described in the TRM section 9.2.9. If you are not getting an accurate ADC conversion result, a common root cause is too short of a sample period.

    Conversion Time

    Conversion time is dependent on the configured resolution and CONVCLK clock frequency (TRM section 9.2.3):

    • 12-bit: 14 CONVCLK cycles
    • 10-bit: 12 CONVCLK cycles
    • 8-bit: 9 CONVCLK cycles

    To adjust the CONVCLK, derived from ADCCLK, see TRM section 9.2.5. Possible clock sources are ULPCLK and SYSOSC, chosen by the SMPCLK field of the ADC CLKCFG register. You will also want to take care to adjust the ADC CLKFREQ register based on the chosen clock settings. You do need to be aware of your reference source. if the internal reference is used, the maximum conversion clock frequency must not exceed 4MHz.

    Thanks,

    Stuart