AM2634: functional description for UART RX FIFO timeout and errata for timeout interrupt

Hello Will,

Additional information on the UART timeout and RX timeout interrupt generation can be found in chapter 13.1.4.4.8.1.5.7.1 Time-Out Counter. 

Will Gao said:

What is difference between timeout and overrun? 

• RX Timeout: An RX idle condition is detected when the receiver line (RX) is high for a time that equals 4x the programmed word length + 12 bits or manually configured amount of baud clocks, if a value other zero is set in the timeout register. RX is sampled midway through each bit
• RX Overrun: occurs if the RX state-machine tries to write data into the RX FIFO when it is already full.

Will Gao said:

In errata, there is an advisory: USART- erroneous clear/trigger of timeout interrupt. What will happen with this error? I know the SDK has implemented the workaround for this error, but customer still wants to know what risk behind this error, if without this workaround. 

The UART module has logic where the timeout interrupt is cleared when RHR/MSR/LSR registers are read. The signal that indicated RHR/MSR/LSR has been read comes from the a different clock domain than the timeout interrupt register.  Since the signal is not synchronized before use, a glitch could erroneously set or clear the timeout interrupt register. 

The risk of not employing the workaround is that the timeout interrupt could potentially be set or cleared when the RHR/MSR/LSR registers are read. 

Regards,

Erik