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TM4C123GE6PM: CPU vs uDMA bus sharing question

Robert Valentine
Prodigy 205 points
Part Number: TM4C123GE6PM
Other Parts Discussed in Thread: EK-TM4C123GXL

Hello,

I have a general question about how the uDMA and CPU share the bus.  I've been reading the datasheet to try to wrap my head around this.  In section 9.2 "Functional Description" shown below it says that the uDMA uses spare CPU cycles.  I'm having trouble getting a good understanding of what this means - especially for a case like ping pong data blocks from say SSI RX FIFO to a chunk of memory which is my use case.

My application has the CPU in a main loop checking variables in memory while the uDMA should be moving data from SSI RS to a memory area with an arbitration size of 4 bytes.  I thought the CPU and uDMA shared the same bus to memory so my questions are below.

1. Does the DMA only access memory when the CPU isn't?  So if I'm constantly polling a flag in RAM will that inhibit the performance of the DMA due to reading the flag (memory location)?

2. How do I know when the CPU is throttling the DMA or vice versa?  I'm confused here as I have read they share one bus but the uDMA often uses spare CPU cycles?

Thanks

  • 0
    TI__Guru**** 191886 points

    Hi Robert,

      I think the below diagram will better assist in understanding of the datapath. Access to SRAM will go through the Bus Matrix. The red path is between DMA and SRAM while the blue path is between CPU and SRAM. CPU can't spend every cycle reading SRAM through System Bus. It also needs to fetch code and data from flash through the ICODE and DECODE bus. Whenever there is a idle cycle available from CPU, DMA will use these cycles to access SRAM. CPU has higher priority than DMA as determined by Bus Matrix. If CPU fully occupies SRAM which I don't perceive to be the case, then DMA has to wait. 

      

  • 0 in reply to Charles Tsai
    Prodigy 205 points

    Hi Charles,

    You support a lot of customers on here!  Thank you!

    So what would the approach for estimating how much access you have for the DMA vs CPU?  Just looking at assembly and compare instruction to/from flash vs SRAM?  It sounds like the DMA performance (how much data it can move in a period of time - say between serial data bursts) is a function of whether the CPU is reading from flash or sram mainly.  If so - do you know how customers get a rough idea of how well the DMA is moving data per some code/loop the CPU is in?

  • 0 in reply to Robert Valentine
    TI__Guru**** 191886 points

    Hi Robert,

      I think the best way would be do empirical experiment. There is already an example at C:\ti\TivaWare_C_Series-2.2.0.295\examples\boards\ek-tm4c123gxl\udma_demo. In this example, it will transfer data between two memory buffers. You can remove other DMA channels that transfer between UART and memory. The example will report the number of bytes transferred. Next you will modify the example to put the CPU in a loop reading data from SRAM constantly and then compare the amount of bytes transferred by DMA.