RTI Interrupt is not occurring while configuring the clock source as PLL

Hi QJ,

Thanks. I configured the clock source as PLL and initialize the respective counter, RTI interreupt not happening. For the same code, i didn't change anything in my code, but i changed the clock source as VCLK, RTI happens perfectly.

void main(void)
{
    /*VIM Init, Interrupt Enable*/
    RTI_irq_int_enable();
    swi_enable_irq();
   
      /** - Call RUN LED routine during the startup */
      run_LED_StartUp();
    
      /** - Initialize SCI Routines to receive Command and transmit data */
      TsInitCommInterface();
     
    rtiInit();
      /** - Configure SCI to receive 8 bytes of Command information */
      //sciReceive(sciREG1, 8, receive_command);
    
         /* Configure the direction as Output. */
    HET_DIR = 0xFFFFFFFF;
    /* Disable Open Drain Capability. */
    HET_PDR = 0x00000000;
    /* Drive the output pins to High */
    HET_DOUT = 0xFFFFFFFF;
    HET_DSET = 0xFFFFFFFF;

    HET_DOUT = 0xFFFFFFFF;
   
   /*VCLK as Clock source selection for RTI*/
      RCLKSRC = 0x00000008U;
   // RCLKSRC = 0x00000001U;     

    rtiREG1->COMPCTRL     = 0x00000000U;
    rtiREG1->SETINT     = 0x00000001U;
    rtiREG1->GCTRL      = 0x00000001U;
       
    /** - Be in infinite Loop waiting for the command from PC/SCI */
  while(1);
 }

This is my main code, in this i changed the lines in bold.

Regards

Gowdham

Hi Gowdham,

Note that the RCLKSRC register allows you to configure any available clock source to be used for the RTI. There is an important constraint that applies when the RTI clock source is not VCLK, and this is that the selected RTI clock source frequency must not be faster than 1/3rd the frequency of VCLK. This constraint is specified on the same page as the description for the RCLKSRC register. The RCLKSRC register allows you to specify the divider that applies when the RTI clock source is selected to be something other than VCLK.

Regards,

Sunil