Other Parts Discussed in Thread: HALCOGEN
The space version of this TI part requires per usage-context proper design and serious code test coverage needs to be done.
TI TRM documentation typically describes peripheral bit-fields by name with a very brief text about it.
Most of the time the bit-fields aren't flagged as configuration or control.
Also some peripheral have engine/state-machine enable controls other don't.
The current documentation isn't complete enough and only expose the basic principle of use and missing the fine prints.
Here is a set of generic questions that pertains to the TRM documentation about all the device peripherals.
It should help understand how poor the documentation is when it comes to exploiting the offering.
Do not answer these but focus on answer the very last question.
Q1) How do we identify the peripherals register bit-fields that addresses configuration from the ones for control ?
(For peripherals with state-machine enable control bit or the ones with reset-state control bit)
Q2) How do we identify the peripherals register bit-fields that we're allowed to modify only when the peripheral state-machine is stopped?
(i.e.: The static configuration)
Q3) How do we identify the peripherals register bit-fields that we're allowed to modify only when the peripheral state-machine is enabled?
(i.e.: The dynamic configuration and control)
Q4) How do we identify the valid order of peripheral control register bit-fields modifications, for proper peripheral control?
And to save time, where are located the real detailed documentation of each peripheral of this device, so we know how to properly configure them, control them once enabled, their limitations, the do and don't at configuration and real-time control?
Regards,
RL
