• Locked Locked
  • Replies 3 replies
  • Subscribers 30 subscribers
  • Views 393 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

HALCoGEN AutoCode Generation

Renjith George
Intellectual 430 points
Other Parts Discussed in Thread: TMS570LS20216, HALCOGEN

Hello,

              I tried the HALCoGen ver 2.07.000 for configuring the RTI module of TMS570LS20216.

1.  After saving the project i tried and generated the files. Imported these generated files into CCS but when trying  to compile - error is shown that "SYS_PRE1" is undefined.  Can anyone suggest why this happens even though i configured the it properly in the HALCoGEN( snapshot added as an attachment) ?

 

2.  Also why this operations  in the statement below when the bits 10 - 31 are all invalid in that register.

 

    /** - Setup RTICLK1 and RTICLK2 clocks */

    systemREG1->RCLKSRC = (1U << 24U)

                        | (SYS_VCLK << 16U)

                        | (0U << 8U) 

                        |  SYS_PRE1;

 

Thanks & Regards,

Renjith George

 

  • TI__Guru**** 197306 points

    George,

     

    SYS_PRE1 should be the clock source selected in “RTI1 PreSrc” box (OSC, or PLL etc).  I will check the HanCoGen expert about the file where SYS_PRE1 is defined.

    Bits16-31 is for RTI2 which doesn’t exist in this device. Sorry for inconvenience.

     

    Regards,

    QJ

     

  • in reply to QJ Wang
    Intellectual 430 points

    Dear QJ,

     

    1. Yes i agree with you that it shall be the clock source selected in RTI1 PreSrc Box.

    From the code in HALCoGen Generated system.c file, the "SYS_PRE1" is "OR"ed into the RCLKSRC register. I feel that should be for bits 3 - 0 of RCLKSRC register.

    0000 Clock source0 is the source for RTI1CLK.
    0001 Clock source1 is the source for RTI1CLK.
    0010 Clock source2 is the source for RTI1CLK.
    0011 Clock source3 is the source for RTI1CLK.
    0100 Clock source4 is the source for RTI1CLK.
    0101 Clock source5 is the source for RTI1CLK.
    0110 Clock source6 is the source for RTI1CLK.

    0111 Clock source7 is the source for RT1ICLK.
    1000–1111 VCLK is the source for RTI1CLK.

    So if i do need the PLL then i shall select  -- 0x0001 (clock source 1 - FMzPLL)


    Clock Source 0 Oscillator
    Clock Source1 PLL1 (FMzPLL)
    Clock Source 2 Not Implemented
    Clock Source 3 Not Implemented
    Clock Source 4 Low Frequency LPO (Low Power Oscillator) clock
    Clock Source 5 High Frequency LPO (Low Power Oscillator) clock
    Clock Source 6 PLL2 (FPLL)
    Clock Source 7 Not Implemented

    Please correct me if i am wrong somewhere.

    Also waiting for your answer after checking with HanCoGen expert regarding where that SYS_PRE1 might be initialised.

     

    2. Thanks for the information. Can we avoid generation of this code when this device is selected, maybe in next version of HALCoGen  ? Hope this will not create any confusions to the reader too .

     

    Thanks & Best Regards,

    Renjith George

  • in reply to Renjith George
    TI__Guru**** 197306 points

    Hi Renjith,

    The new HalCoGen 2.11 fixed the issues you mentioned. SYS_PRE1 is also defined in the header file.

    Regards,

    QJ