TMS570LS1224: Can I use the 2-Data Line mode with MIBSPI1

Hi Glenn,

Glenn Graf said:

My need is to clock (SPI) data in from pin #105 (PGE QFP)  (configured as MIBSPI1SOMI[1]) rather than from pin #94 MIBSPI1SOMI[0] .Is there any way to accomplish this? 

This is not possible, i mean even MibSPI supports 2-data line mode but your requirement to clock data only from MIBSPI1SOMI[1] is not possible.

I will explain how exactly 2-data line mode will work:

Basically the parallel data line modes will increase data rate.

For example:

1-bit data line mode means you can send/receive 1- data bits for every SPI clock cycle

2-bit data line mode means you can send/receive 2- data bits for every SPI clock cycle

4-bit data line mode means you can send/receive 4- data bits for every SPI clock cycle

So the below diagram will show how 2-data line mode will work.

For example if you write a 16 bit data into the shift register, then as you can see before giving any clock SIMO[1] will point to the 15th position of the shift register and SIMO[0] will point to the 7th position of the shift register right, now if SPI clock of 1st cycle received then the 15th bit of the shift register will move on to the SIMO[1] and 7th bit of the shift register will get move on to the SIMO[0], as soon as this shift is done SIMO[1] will now point to the 14th bit of shift register(because data got shifted) and SIMO[0] will point to the 6th bit of the shift register. And as soon as SPI clock of 2nd cycle received then the 14th bit of the shift register will move to the SIMO[1] and 6th bit of the shift register will get move on to the SIMO[0]. And this operation will continue till all 16 bits of shift register will moved to the SIMO[1] and SIMO[0] with 8 bits each(that means the higher byte of data is moved to the SIMO[1] and lower byte of the data is moved on to the SIMO[0]). This is the operation will see on the transmitter end of 2-bit line mode.

If we see the receiver operation it is exactly in reverse like, SOMI[1] will point to the 8th position of the shift register and SOMI[0] will point to the 0th position of the shift register, so you know that data will come like most significant bit first right, that is 15th bit to the 8th bit on the SOMI[1] and 7th bit to the 0th bit on the SOMI[0] right. So as soon as first SPI clock received then the 15th bit will moved to the 8th position of the shift register and 7th bit will moved to the 0th position of the shift register. As soon as 2nd SPI clock received then the 15th bit in the 8th position will get shifted to the 9th position and new 14th bit received will be moved to the 8th position from SOMI[1] and similarly the 7th bit of the 0th position will get moved to the 1st position and new data bit of 6 will get moved to the 0th position the shift register from SOMI[0]. And this operation will get continued till you received total 16 bits and 8 bit each on SOMI[1] and SOMI[0].

In conclusion in parallel data line mode you can't use any single line to received data or transmit data. If you want to use single line receive/transmit then you should use SOMI[0]/SIMO[0] respectively for master mode.

--

Thanks & regards,
Jagadish.