Other Parts Discussed in Thread: AM2732
According to the C66x DSP Cache User Guide, DMA reads / writes to L2 memory trigger a cache coherency mechanism which makes invalidation / writeback superfluous when dealing with local (L2) memory.
In the MCU+ SDK (AM2732) EDMA link-transfer example, however, cache coherence is explicitly used:
- Cache writeback is initially done on buffers after initialization by the core (cf. edma_link_transfer.c:136 in MCU+ SDK 8.5.0.24 link transfer EDMA example)
- After the EDMA test transfer, cache invalidate is done on the buffer written by EDMA before checking the result (= reading from CORE) (cf. edma_link_transfer.c:223)
In the example, everything is allocated in DSS_L2 which means that the stack (including the buffers) are in L2 RAM. This seems to make these cache coherency operations superfluous.
I can see a number of reasons why the code would be written this way (if the code is copy pasted in a project using L3 for example), but since invalidation / writebacks tank performance in real applications, I wanted to make sure that these coherency operations are superfluous in this SDK example.
