AM2634: Software example to start slave core

Hi Tareq,

Can you elaborate more about your request? Do you mean That R5F_0_0 to bootload and start programs on R5F_0_1, R5F_1_0, R5F_1_1, or the lock step for R5F 0_0 and R5F_0_1?

Best regards,

Ming

Yes R5F_0_0 is already up and from software I want to start other cores so it can executes its software 
for example to start  R5F_1_0,R5F_1_1

My use case that I will flash the elf on all cores but I want R5F_0_0 only to start at first and then from R5F_0_0  software it unhalt the other cores. Is this possible ?
If so how ? is this related to WFI also ?

This because I am running an AUTOSAR application and in AUOTSAR the master core should trigger the start for the remain cores

That's great can you guide my where I can find the part related to "and then start each core one by one" 
Nore: I am developing AUTOSAR OS using different debugger and I am not using SDK examples 

Thanks Ming for your reply. This is provided some insights 

As I mentioned I am developing an operating system and in my testing environment I am not using SBL so T32 scripts helps me to boot  R5F_0_0 core and I guess what I need to do in my software is to unhalt the other cores like the example sbl_qspi (The software is fleshed in other cores also by T32 scripts)
I tried to do so but unhalt do nothing and software in other core still stuck in its entry point. 
Not sure if they already in WFI state or not. 
I have read the link: AM263x MCU+ SDK: Understanding the bootflow and bootloaders (ti.com)
It mentions "the very first thing it does is detect the core and continue execution for Core0, while if the core is Core1 then it enters wfi loop."
how entering  wfi loop is done in this case ? note that MSS_CTRL_R5SS0_FORCE_WFI register is global for whole R5SS0.

Hi Tareq,

I will forward this thread to our expert in bootloading for further help!

Best regards,

Ming

Yes WFI stat is 1

Hi Tareq,

Are you using DEV Boot Mode ? In that case you can control all the initialization via Debugger. If you are doing all the initialization via debugger, can you share your .cmm file ?

Best Regards,
Aakash

I am using QSPI mode but I am flashing all my application in RAM as this is enough for testing purposes. 
How can I send you the cmm scripts as I cannot see an attachment option here 

This an inital example trying to run R5F_SS0 as dual core where core0 is the master and core 1 is the slave core

LOCAL &parameter_list
ENTRY %LINE &parameter_list

DO "~~~~/scripts/AM263x.cmm" ; enable all power & clocks & load menus
DO "~~~~/scripts/AM263x.cmm" R5F_SS0_Dual_Core_RAM_boot
DO "~~~~/scripts/AM263_Common.cmm" R5F_SS0_POR_Reset

RESet
SYNCH.RESet
SYStem.RESet

IF COMBIPROBE()||UTRACE()
SYStem.CONFIG.CONNECTOR MIPI34 ; because of converter LA-3782

SYStem.Option RESBREAK OFF
SYStem.Option EnReset OFF
SYStem.JTAGCLOCK CTCK 10MHz

SYStem.MemAccess.DAP
SYStem.Option.imaskasm.on
SYStem.Option.IMASKHLL.ON

TPIU.PortMode.Continuous
IF !SIMULATOR()
trace.method.Onchip

&intercomport_core0=FORMAT.DECIMAL(1.,intercom.port())
&intercomport_core1=FORMAT.DECIMAL(1.,intercom.port()+1)

&core0="intercom localhost:&intercomport_core0"
&core1="intercom localhost:&intercomport_core1"
&allcores="GOSUB intercom_allcores "

; set titles
&core0 Title "CORE0"
&core1 Title "CORE1"

&core0 area.create A000 100 1000
&core0 area

&core1 area.create A000 100 1000
&core1 area

&core0 SYStem.Mode Down
&core0 SYStem.CPU Am2634-SS0
&core0 core.assign 1
&core0 SYStem.Mode Attach
&core0 break
&core0 Register.Init

&core1 SYStem.Mode Down
&core1 SYStem.CPU Am2634-SS0
&core1 core.assign 2
&core1 SYStem.Mode Attach
&core1 break
&core1 Register.Init

;Disable MPU
&core0 Data.Set C15:0x1 %long (Data.Long(C15:0x1)&(~0x1))
&core1 Data.Set C15:0x1 %long (Data.Long(C15:0x1)&(~0x1))

;Load elf
&core0 data.load.elf &parameter_list
&core1 data.load.elf &parameter_list

;Turn Off Vector Catches
&core0 TrOnchip.Set.FIQ OFF
&core0 TrOnchip.Set.IRQ OFF
&core0 TrOnchip.Set.DABORT OFF
&core0 TrOnchip.Set.PABORT OFF
&core0 TrOnchip.Set.SWI OFF
&core0 TrOnchip.Set.UNDEF OFF
&core0 TrOnchip.Set.RESET OFF

&core1 TrOnchip.Set.FIQ OFF
&core1 TrOnchip.Set.IRQ OFF
&core1 TrOnchip.Set.DABORT OFF
&core1 TrOnchip.Set.PABORT OFF
&core1 TrOnchip.Set.SWI OFF
&core1 TrOnchip.Set.UNDEF OFF
&core1 TrOnchip.Set.RESET OFF


; Enable run time accesses to R5 TCMs
&core0 DO "~~~~/scripts/am263_runtime_memory_access.cmm"


R5F_SS0_Dual_Core_RAM_boot:
(
DO "&path_AM263_common_cmm" MSS_CTRL_unlock
ENTRY &__V7
DO "&path_AM263_common_cmm" MSS_TOPRCM_unlock
ENTRY &__V8
DO "&path_AM263_common_cmm" MSS_RCM_unlock
ENTRY &__V9
DO "&path_AM263_PLL_cmm" Config_R5FCLK_400M_SYSCLK_200M
ENTRY &__V10
GOSUB En_All_Peripheral_Clks
DO "&path_AM263_common_cmm" R5F_SS0_Reset
ENTRY &__V12
DO "&path_AM263_common_cmm" R5F_SS1_Reset
ENTRY &__V13
DO "&path_AM263_common_cmm" R5F_ROM_eclipse
ENTRY &__V14
DO "&path_AM263_common_cmm" R5F_SS0_CoreA_unhalt
ENTRY &__V15
DO "&path_AM263_common_cmm" R5F_SS0_CoreB_unhalt
ENTRY &__V16
DO "&path_AM263_common_cmm" R5F_SS1_CoreA_unhalt
ENTRY &__V17
DO "&path_AM263_common_cmm" R5F_SS1_CoreB_unhalt
ENTRY &__V18
PRINT ""
PRINT ""
PRINT " ***All R5F cores are in Dual core RAM boot mode*** "
PRINT ""
PRINT ""
RETURN
)

R5F_SS0_POR_Reset:
(
GOSUB Write_MMR (&__MSS_RCM_U_BASE+&__MSS_RCM_R5SS0_POR_RST_CTRL) 0x7
GOSUB Write_MMR (&__MSS_RCM_U_BASE+&__MSS_RCM_R5SS0_POR_RST_CTRL) 0x0
PRINT ""
PRINT "*R5FSS0 POR Complete*"
PRINT ""
RETURN

)

R5F_SS0_Reset:
(
GOSUB Write_MMR (&__MSS_RCM_U_BASE+&__MSS_RCM_R5SS0_RST2ASSERTDLY) 0x0
GOSUB Write_MMR (&__MSS_RCM_U_BASE+&__MSS_RCM_R5SS0_RST_WFICHECK) 0x00000707
GOSUB Write_MMR (&__MSS_CTRL_U_BASE+&__MSS_CTRL_R5SS0_CONTROL) 0x707
GOSUB Write_MMR (&__MSS_CTRL_U_BASE+&__MSS_CTRL_R5SS0_CONTROL) 0x700
GOSUB Write_MMR (&__MSS_CTRL_U_BASE+&__MSS_CTRL_R5SS0_CONTROL) 0x70700
GOSUB Write_MMR (&__MSS_CTRL_U_BASE+&__MSS_CTRL_R5SS0_FORCE_WFI) 0x7
PRINT ""
PRINT ""
PRINT "***R5FSS0 Reset Complete***"
PRINT ""
RETURN

)

R5F_ROM_eclipse:
(
GOSUB Write_MMR (&__MSS_CTRL_U_BASE+&__MSS_CTRL_R5SS0_ROM_ECLIPSE) 0x7
PRINT "R5F ROM Eclipse"
PRINT ""
RETURN

)

R5F_SS0_CoreA_unhalt:
(
GOSUB Write_MMR (&__MSS_CTRL_U_BASE+&__MSS_CTRL_R5SS0_CORE0_HALT) 0x00000000
PRINT "R5FSS0_0 Released"
PRINT ""
RETURN

)

R5F_SS0_CoreB_unhalt:
(
GOSUB Write_MMR (&__MSS_CTRL_U_BASE+&__MSS_CTRL_R5SS0_CORE1_HALT) 0x00000000
PRINT "R5FSS0_1 Released"
PRINT ""
RETURN

)

R5F_SS1_CoreA_unhalt:
(
GOSUB Write_MMR (&__MSS_CTRL_U_BASE+&__MSS_CTRL_R5SS1_CORE0_HALT) 0x00000000
PRINT "R5FSS1_0 Released"
PRINT ""
RETURN

)

R5F_SS1_CoreB_unhalt:
(
GOSUB Write_MMR (&__MSS_CTRL_U_BASE+&__MSS_CTRL_R5SS1_CORE1_HALT) 0x00000000
PRINT "R5FSS1_1 Released"
PRINT ""
RETURN

)

Also can you tell me the relation between WFI and unhalting the core, Does unhating the core means that it will get out of WFI state?
Also I note that MSS_CTRL_R5SSx_COREx_HALT is always 0 (unhalted) for all cores no matter what (even I did not unhalt the core in the script) so do you have any idea why ?

I am asking these question because I am designing the OS and what I need that only the master core (R5SS0_0) runs first, all other cores are in halt/waiting state and then from Master core software I trigger the other cores to run.
But I cannot achieve this as I cannot understand the relation between halt/WFI and why the cores is always seems unhalted.

Hello Tareq,

Allow me some time to find accurate answers to your questions. In the mean time, would it be possible to link your complete .cmm file? This can be done by selecting "Insert" -> Image/video/file.

Regards,

Erik

T32-Script.zip

The entry point script is T32_PROG_C2_AM263x.cmm

Hello Tareq,

Thank you for sharing the .zip. I will be able to test and review it by tomorrow end of day. 

The R5SS has three power states: Off, active, and standby. STANDBY mode refers to when there is a WFI or WFE instruction and the core hangs until there is work that wakes the core in the form of an IRQ. 

The core HALT keeps the cores from fetching instructions when they come out of reset. The main use of this is to have the cores halted until the TCMs are loaded (when booting from the TCM), though halt could be used for other purposes. 

Regards,

Erik

Hello Erik 
Thank you for your reply and waiting your feedback regarding the sent scripts. Note that in addition to these scripts after that in master core in C code I try to unhalt other cores but nothing happens as I mentioned before. 
So could unhating be used to release the other cores from the halt state ? Because In my case nothing works in c code to release the slave cores

Hello Erik,

Thank you for your clear effort

Adding the script lines you have provided in last comment made the Core 1 (the slave core) to start directly after running the scripts.
But this is not the desired behaviour.

We wish that after running the scripts core 1 (slave core) is in halt state (not running) and Master core from SW we unhalt this slave core.
Seems that writing into MSS_CTRL_R5SS1_CORE0_HALT register is not doing anything in all cases.

I tried so many scenarios like trying to put the slave core in halt state by the scripts and unhating it through  MSS_CTRL_R5SS1_CORE0_HALT in master core SW but seems this register not doing anything in any case. 

What actually worked for me is using  MSS_R5SS1_CORE0_LRST_CTRL in Master core SW to reset R5SS1_CORE0 at certain point via writing 0x1 into MSS_R5SS1_CORE0_LRST_CTRL. Hence R5SS1_CORE0 start running as expected.

But the problem that in datasheet in mentions that MSS_R5SS1_CORE0_LRST_CTRL is for debug purpose only so I guess I cannot use it in my SW and deliver it to my customer to be used in production later on.



So if this register really for debug purpose only? or it is a documentation glitch ?
If it is really for debugging so that is its alternative ? 

Hello Tareq,

• Ideally you should only use the FSM trigger POR reset to reset the dual CPU cluster. This needs to be done even if both CPU's are in WFI/HALT state.
• The HALT signal will only work when the CPU is in reset
  • The intent of the signal is to keep the CPU in halt when it is taken out of reset. This enables another corre to load into its TCM and then remove the HALT
  • The HALT signal will not work on a running core - as you are observing
• The CPU will enter WFI when it executes a WFI instruction
  • This is reflected in the MMR status in MSS_CTRL
  • The MMR also indicated a WFI when the HALT MMR is set. In this case this is not a true WFI since it is only set due to the HALT MMR being set. 

Here is the expected flow for what you are trying to accomplish:

1. All CPU cores are in HALT state out of chip reset
2. The HSM ROM will unhalt the R5SS CORE0 and R5 ROM runs. The other cores continue to be in HALT state (but out of reset).
3. The R5 ROM loads SBL and trigger FSM Reset (after a WFI on Core0). This resets the R5SS0 Cluster. Since the R5SS0CORE0 MMR is not in halt state, it will run. The other three cores continue to be in a HALT state.
4. R5SS0 CORE0 runs the SBL.
5. Now the SBL can load the TCM of other cores and remove the HALT signal of the other three cores. 

Core reset should not be needed but rather just unhalting the cores after loading the code. 

Regards,

Erik