All,
I have a customer who is bit banging an I2S bus. He is very close to making it work. I would love to see him succeed as a prototype for others. He writes:
I have configured the SPI in TI sync mode at 16bits and reload 1 word by polling on TX fifo empty. Can do TX Fifo update by interrupt, but not needed right now.
At TX fifo 1 word load I toggle a PORT pin to emulate I2S LRCLOCK function, and on the scope the Ms bit timing is offset but stable, and clock is continuous.
The issue is that many I2S devices need a positive clock edge, i.e. data out on PICO changes on falling edge for setup before rising clock, but TI sync mode shifts data on positive/rising edge which is a race condition on many setup/hold times.
The MSPM0L part shows the IOMUXnn.26 is the INV bit for I/O but this is not shown on the MSPM0G3507 FRM on IOMUX. The G3507 FRM IOMUX text and diagram mention the INV bit, but is not present in the FRM IOMUXnn.26 in register definitions and .h file.
If I can invert this SPICLK drive out then I can bodge a I2S function by simply offsetting consecutive words with 2 ms/ls bits to put everything in correct phase with LRCLOCK, so it will work fine. With 32 bit shifter its trivial to skew to realign the consecutive 16bit I2S data words.
Can you confirm if IOMUXnn register bit 26 acts as the INVERT i/o control on MSPM0G3507, or if this was stripped from e.g. eval parts?
Its hard to imagine the MSPM0G part silicon net-list would drop what was designed into the slower MSPM0L cousin part...
Best Regards,
Blake
