Hello,
We are developing a project that needs to perform in parallel:
* High speed acquisition of ADC, connected on SPI bus
* Events logging to a SPI flash.
The high speed ADC acquisition shall be done periodically, without jitter, while events logging to flash can be performed at lower priority, and eventually be interrupted if an higher priority ADC period occurs before all transfers of flash storage are done
According to TMS570LC43x datasheet spnu563a.pdf, p706, it could be possible to assign the flash storage transfers as low priority and ADC as high priority.
We would like to know if:
When an high priority DMA is pending
It can interrupt an on-going low priority DMA transfer before all transfers are completed in order to service the high priority DMA transfer
