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TM4C1294NCPDT: Memory control is verified by connecting SDRAM and QSPI-FlashROM to TM4C1294NCPDT.

Conor
Guru 12115 points
Part Number: TM4C1294NCPDT

Hi,

Memory control is verified by connecting SDRAM and QSPI-FlashROM to TM4C1294NCPDT.

Q1
When using EPI0S as an address bus and data bus, is it necessary to process a pull-up resistor, etc.?

Q2
Is it necessary to process the pins of the memory control lines assuming that they operate in SDRAM mode?

Q3
Connect to SSI of TM4C1294 for QSPI-FROM connection. Is terminal processing necessary in this case?

In either case, we are concerned about the behavior of the TM4C1294 pins when the following events occur.
(a) When power is turned on
(b) Immediately after hard reset
(c) Common to (a) and (b), after that, the software starts running and the GPIO pin assumes a predetermined role

Thanks,

  • 0
    TI__Guru**** 191266 points

    Hi,

    Conor said:

    Q1
    When using EPI0S as an address bus and data bus, is it necessary to process a pull-up resistor, etc.?

    Q2

    No. That is not necessary.

    Conor said:

    Q2
    Is it necessary to process the pins of the memory control lines assuming that they operate in SDRAM mode?

    Q3
    Connect to SSI of TM4C1294 for QSPI-FROM connection. Is terminal processing necessary in this case?

    I'm not sure what you mean by process the pins of the memory control lines. 

     Please take a look at this TI Reference Design. https://www.ti.com/tool/TIDM-TM4C129SDRAMNVM.   This design should run code out of SDRAM. The software collateral is missing in the design page but I'm attaching here. 

    TIDM-TM4C129SDRAMNVM.zip

    There is also a SDRAM example in C:\ti\TivaWare_C_Series-2.2.0.295\examples\peripherals\epi\sdram.c on how to configure EPI pins if this is what you refer to as process the memory control lines. 

    Conor said:
    (a) When power is turned on
    (b) Immediately after hard reset
    (c) Common to (a) and (b), after that, the software starts running and the GPIO pin assumes a predetermined role

    After a power cycle and a reset, the EPI must be initialized first before you can access the SDRAM. The GPIO pins must be configured for EPI pins for SDRAM operation.