TMS570LC43x SAFETI

Hi Pankaj,

Can you please refer below two threads?

(+) RM57L843: SAFETI_DIAG_LIB Hercules SafeTI︎ Diagnostic Library Issue - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

In above thread they are suggesting to enable Auto ECC Generation.

(+) LAUNCHXL2-RM57L: Hercules SafeTI︎ Diagnostic Library V2.4.0 demo application stuck at clearing ESM error - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

In above thread they are identified one bug in diagnostic library.

--

Thanks & regards,
Jagadish.

HI Jagadish,

Thanks for your valuable reply.

I have put sl_esmREG->EKR = 0xAu in _SL_HoldNClear_nError(void) function.

Q1. Now it is come out from while loop. but my question is is this correct to put 0x0A in ESM EKR resister? 

Q2. Now I am  have stuck in esmREG->SSR2 register is showing  0x00000004. it is showing CPU Compare error in group2.

How we can resolve this issue?

HI Jagadish,

We are unable to find solution in run safeTI library it is showing unexpected behaviour.

1. Some time it is stuck in esmREG->SR[0] != 0 condition 

2. Some time code is stuck in below while(1) loop

if(esmREG->SSR2 == 0u)
{
SL_SelfTest_STC(STC1_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);
}
else
{
while(1); //ESM Group2 error
}

3. some time code is reset ad come in SL_Init_R5Registers();

Please help us how to run whole program and check diagnostic errors and also sequence document which is relate to code flow.

Pankaj Verma said:

1. Some time it is stuck in esmREG->SR[0] != 0 condition

esmREG->SR[0] != 0 should not cause the code stuck.

Pankaj Verma said:

2. Some time code is stuck in below while(1) loop

Is esmREG->SSR2 - 0x00000004 which means CCM-R5F-CPU compare error?

TMS570LC43x includes dual Cortex-R5F CPUs running in a lock-step operation mode. A core compare module (CCM-R5F) compares the output signals from each R5F CPU. Any difference in the two CPUs’ outputs is flagged as a fault of a high-severity level. The CPU internal registers are not guaranteed to power up in the same state for both the CPUs. The CPU pushes the internal registers on to the stack on a function call, which could lead to the detection of a core compare error. Therefore, the CPU internal core registers need to be initialized to a predefined state before any function call is made.

Pankaj Verma said:

3. some time code is reset ad come in SL_Init_R5Registers();

Do you mean that SL_Init_R5Registers() resets the device? What is the value of systemREG1->SYSESR?

Hi QJ Wanj,

Thankyou for you replay

Below are the Answer 

QJ Wang said:

1. esmREG->SR[0] != 0 should not cause the code stuck

Ans:- i have put this line  "esmGroup3Notification(esmREG,esmREG->SR1[2]);" instead of while(1); 

if ((esmREG->SR1[2]) != 0U)
{
// while(1); //ESM group3 error
esmGroup3Notification(esmREG,esmREG->SR1[2]);
}

If this error is occurred what we have to do to solve this error and how we know which error is this and how to solve it "Any document it will be very helpful". 

why i am asking this question because i am using TMS570LC43x HERCULES DEVELOPMENT KIT and SAFETI library using demo code 2.4.0 or 2.3.2 code.

and i hope EVK and demo code should work properly and see the diagnostic result, and how we can implement in our application.

QJ Wang said:

2. Do you mean that SL_Init_R5Registers() resets the device? What is the value of systemREG1->SYSESR? 

Ans:- No i am not saying SL_Init_R5Registers() resets the device, i am saying that after come to SL_Init_ResetReason(); function and if i am run code then iit will come to SL_Init_R5Registers() due to some reset condition.

What is the value of systemREG1->SYSESR -----> the value is 0x00000800.

If this error is occurred what we have to do to solve this error and how we know which error is this and how to solve it "Any document it will be very helpful". 

QJ Wang said:

3. Ok due to the difference in two CPUs’ outputs is flagged as a fault and core compare error is generated, than what we need to do to solve this problem and if any other error is come regarding any GROUP1/2/3 how we solve it.

4. Most of time code is hang in below while(1) condition because of "TYPE_DEBUG != resetReason" 

/* ensure no pending ESM GRP2 errors before running STC */
if(esmREG->SSR2 == 0u)
{
SL_SelfTest_STC(STC1_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);
}
else
{
while(1); //ESM Group2 error  stop here always.
}

QJ WANG Please help us how to run whole program and check diagnostic errors and also sequence document which is relate to code flow.

Hi QJ Wang and Jagadish,

I have investigate more on it and i have seen that the initial value sl_systemREG1->SYSESR; register is 0x00000800 and resetReason is RESET_TYPE_DEBUG.

when we are entering inside a SL_Init_Memory(RAMTYPE_RAM); function, after execution of sl_systemREG1->MSINENA  = ramSet; instruction than the value of  sl_systemREG1->SYSESR; register is also changed from "0x00000800" to "0x00000000" due this the resetReason is also change from "RESET_TYPE_DEBUG" to "RESET_TYPE_UNKNOWN".

Why the value of sl_systemREG1->SYSESR changing after execution of  sl_systemREG1->MSINENA  = ramSet instruction?

Regards,

Pankaj Verma

SL_Init_Memory(RAMTYPE_RAM) will not cause reset.

The SYSESR register is cleared to 0x0000 after SL_Init_ResetReason() is called.

Thank you for your reply. As your reply we saw that we are not calling SL_Init_ResetReason() again "only one time call"

But the result was same resetReason is changed after calling SL_Init_Memory(RAMTYPE_RAM); function 

For your reference:-

resetReason = SL_Init_ResetReason();                <--   Initially resetReason value is "RESET_TYPE_UNKNOWN"

                                               
switch(resetReason)                                                    <--   resetReason value is "RESET_TYPE_DEBUG"
{
case RESET_TYPE_POWERON:
case RESET_TYPE_DEBUG:
case RESET_TYPE_EXTRST:
case RESET_TYPE_EXTRST_NERROR:

SL_Init_Memory(RAMTYPE_RAM);                        <--  Till here  resetReason value is "RESET_TYPE_DEBUG" which is correct 

/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_SL_Init_EnableEventExport();                              <-- Again  resetReason value changed "RESET_TYPE_UNKNOWN"

/* USER CODE END */

/* Check if there were ESM group3 errors during power-up.
* These could occur during eFuse auto-load or during reads from flash OTP
* during power-up. Device operation is not reliable and not recommended
* in this case. */
if ((esmREG->SR1[2]) != 0U)
{
// while(1); //ESM group3 error
// esmGroup3Notification(esmREG,esmREG->SR1[2]);
}

/* Initialize System - Clock, Flash settings with Efuse self check */
systemInit();

}

////////////////////////////////////////////////

After this 

/* USER CODE BEGIN (22) */
if(RESET_TYPE_DEBUG != resetReason)                                                         <--  Till here  resetReason value is "RESET_TYPE_UNKNOWN"
{
if(RESET_TYPE_ICSTRST != resetReason)
{
/* Memory interconnect selftest */
SL_SelfTest_MemoryInterconnect(MEMINTRCNT_SELFTEST);
}

/* Make sure that the CPU self-test controller can actually detect a fault inside CPU */
stcSelfTestConfig.stcClockDiv = 0; /* STC Clock divider = 1 */
stcSelfTestConfig.intervalCount = 1; /* One interval only */
stcSelfTestConfig.restartInterval0 = TRUE; /* Start from interval 0 */
stcSelfTestConfig.timeoutCounter = 0xFFFFFFFF; /* Timeout counter*/
_SL_HoldNClear_nError();

/* mask vim interrupts before running STC */
vimREG->REQMASKCLR0 = 0xFFFFFFFFu;
vimREG->REQMASKCLR1 = 0xFFFFFFFFu;
vimREG->REQMASKCLR2 = 0xFFFFFFFFu;
vimREG->REQMASKCLR3 = 0xFFFFFFFFu;
/* ensure no pending ESM GRP2 errors before running STC */
if(esmREG->SSR2 == 0u)
{
SL_SelfTest_STC(STC1_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);
}
else
{
while(1); //ESM Group2 error                                   <-- Due to  resetReason value is "RESET_TYPE_UNKNOWN" We are always in While one only.
}

}
else
{
afterSTC();                                     <-- If the  resetReason value is "RESET_TYPE_DEBUG" than only code will call this function which is not                                                                        happen
}
}

Please see why this is happen, Is there any changes in code we need?

Hi Pankaj,

Please check if the following methods can resolve the issue:

1. Initialize the MCU SRAM before checking the reset resource:

    SL_Init_R5Registers();

    SL_Init_StackPointers();

    SL_Init_Memory(RAMTYPE_RAM);

    _SL_Init_EnableEventExport();

    resetReason = SL_Init_ResetReason();

    switch(resetReason)
    {

           .....

     }

2. Declare the resetReason as register. The keyword 'register' means that the variable is stored in a processor register instead of memory.

    register resetSource_t   rstSrc;
    rstSrc = SL_Init_ResetReason();

    switch(rstSrc)

Thanks for your valuable reply.... 

Due to these changes the resetReason is not change and it is going into main () function.

Issue is below now

main()

{

while(1)                                       <-- Coming her properly

{
maintaskcount++;                     <-- Coming her properly and run while loop  10 times
if(maintaskcount>10)
{

#ifdef __TI_COMPILER_VERSION__
__asm(" b #-8 ");                                                <-- code is hang in this inline instruction.
#endif

....

}

......

}

Q1. Can you please tell us what is the meaning of this inline instruction?

Q2. Is this neccessary to run or we can comment it out?

Q3. where we are define  __TI_COMPILER_VERSION__ ?

Q4. where we can get/store the data  of below code?

#if FUNCTION_PROFILING_ENABLED
fptests = fopen("Profile_tests.txt","w+");                                                        <-- Q4 where is located Profile_tests.txt file "i did not found in folder" ?
fppbisttests = fopen("Profile_pbist_tests.txt","w+");
if ((fptests == NULL)||(fppbisttests == NULL)) {
printf("Can't open files for writing!\n");
}
else
{
printf("Hi!\n");

fputs("testype\tlastentrytick\tlast_exittick\terror_creation_tick\texecution_count\tcumilative_execution_tick\tesm_entrytick\tesm_exittick\taborthandler_entrytick\taborthandler_exittick\n",fptests);

for(i =0;i<(TESTTYPE_MAX - TESTTYPE_MIN);i++)
{

fprintf(fptests,"%s\t",stringFromTestType(i));
fprintf(fptests,"%d\t",SL_Profile_Struct[i].last_entrytick);                                       <-- Q5 how we can enable printf in CCS IDE? 
fprintf(fptests,"%d\t",SL_Profile_Struct[i].last_exittick);
fprintf(fptests,"%d\t",SL_Profile_Struct[i].error_creation_tick);
fprintf(fptests,"%d\t",SL_Profile_Struct[i].execution_count);
fprintf(fptests,"%d\t",SL_Profile_Struct[i].cumilative_execution_tick);
fprintf(fptests,"%d\t",SL_Profile_Struct[i].esm_entrytick);
fprintf(fptests,"%d\t",SL_Profile_Struct[i].esm_exittick);
fprintf(fptests,"%d\t",SL_Profile_Struct[i].aborthandler_entrytick);
fprintf(fptests,"%d\n",SL_Profile_Struct[i].aborthandler_exittick);
}

fclose(fptests);

fputs("ramgroup\talgoinfo\tlast_entrytick\tlast_exittick\ttexecution_count\tcumilative_execution_tick\n",fppbisttests);
for(i =0;i<PBIST_MEM_MAX;i++)
{
for(j =0;j<PBIST_ALGO_MAX;j++)
{

fprintf(fppbisttests,"%s\t",stringFromramgroup(i));
fprintf(fppbisttests,"%s\t",stringFromalgo(j));
fprintf(fppbisttests,"%d\t",SL_Pbist_Profile_Struct[i][j].last_entrytick);
fprintf(fppbisttests,"%d\t",SL_Pbist_Profile_Struct[i][j].last_exittick);
fprintf(fppbisttests,"%d\t",SL_Pbist_Profile_Struct[i][j].execution_count);
fprintf(fppbisttests,"%d\n",SL_Pbist_Profile_Struct[i][j].cumilative_execution_tick);
}
}
fclose(fptests);

}
for(i=0;i<10000;i++); //wait for fprintf to complete
__asm(" b #-8 ");                                                   <-- why is this using?
#endif

}

Pankaj Verma said:

Q1. Can you please tell us what is the meaning of this inline instruction?

This instruction is same as while(1) in C/C++.

Pankaj Verma said:

Q2. Is this neccessary to run or we can comment it out?

Yes, you can comment it out.

Pankaj Verma said:

Q3. where we are define  __TI_COMPILER_VERSION__ ?

It is a predefined ARM Macro Name. 

Pankaj Verma said:

Q4. where we can get/store the data  of below code?

The profiling of the functions is not enabled by default. Is it enabled in your project? Did you check the Debug folder?

Hi Wang,

I have already enabled the "FUNCTION_PROFILING_ENABLED" macro.

But i did not find any "Profile_tests.txt" file inside the debug folder.

I have an one queries that:-

inside the  void afterSTC(void) function. If i am getting any of one "RAMTYPE_MIBSPI2_RAM" failure. 

/* Initialise MIBSPI SRAM */
SL_Init_Memory(RAMTYPE_MIBSPI1_RAM);
SL_Init_Memory(RAMTYPE_MIBSPI2_RAM);
SL_Init_Memory(RAMTYPE_MIBSPI3_RAM);
SL_Init_Memory(RAMTYPE_MIBSPI4_RAM);
SL_Init_Memory(RAMTYPE_MIBSPI5_RAM);

and If the status bit of  MSTDONE is not set than how we will solve this problem.

We want to re run this test case again. what we have to do?

If you having any document regarding error solving of particular test failure please let us know. it will be very helpful for us.

Thanks and regard

Pankaj Verma

Pankaj Verma said:

We want to re run this test case again. what we have to do?

The auto-init can be disabled by writing 0x5 to MINITGCR register, then re-enabled (writing 0xA to MINITGCR). 

Pankaj Verma said:

But i did not find any "Profile_tests.txt" file inside the debug folder.

I will check this

Hi Wang,

Thanks for your quick replay.

I am facing one more issue that:

I am using this safeTI library with RTOS.

I have found that the scheduler is not initialize due to CPSR register is in supervisor mode (0x13).

If we want to initialize RTOS scheduler properly we need to run core in user/system mode (0x1F).

In safeTI code is always run in  supervisor mode (0x13). I have tried to change the mode from  supervisor mode (0x13) to user/system mode (0x1F) in stack pointer assembly function SL_Init_StackPointers(); 

But it is changing the mode if i am debugging in assembly code, but it will giving software reset after SL_ESM_Init(ESM_ApplicationCallback); and than code is going to reset and give resetReason is in software reset mode. 

Can you help me that how and where we can change mode from supervisor mode to user mode for successfully safeTI initialization done and for schedular initializing properly.

Important: 

1. it is necessary to run safeTI  all test (before main and after main) in supervisor mode (0x13)?

2. where we can change the mode from supervisor mode (0x13) to user/system mode (0x1F)?

Thanks and regard

Pankaj Verma

Hi Wang,

I have checked that the

SL_Init_Memory(RAMTYPE_MIBSPI1_RAM);                                    <-- successfully done status here

here the value in MINITGCR register is 0x0A
SL_Init_Memory(RAMTYPE_MIBSPI2_RAM);                                   <-- Hung here due to status bit of  MSTDONE is not set 

SL_Init_Memory(RAMTYPE_MIBSPI3_RAM);                                        <-- successfully done status here

here the value in MINITGCR register is 0x0A

SL_Init_Memory(RAMTYPE_MIBSPI4_RAM);                                    <-- Hung here due to status bit of  MSTDONE is not set 

SL_Init_Memory(RAMTYPE_MIBSPI5_RAM);                                      <-- successfully done status here

The value of here the value in MINITGCR register is 0x0A inn all the test cases

Thanks and regard

Pankaj Verma

Hi Pankaj,

1. Could you please double check that the TMS570LC43x or RM57L8x is used in your test? TMS570LSx devices don't support MibSPI2 and MibSPI4.

2. Please check if MibSPI2 and MibSPI4 RAM groups are declared correctly (group 18 and group 19):

sl_types.h:

RAMTYPE_MIBSPI2_RAM = 0x00040000u,/**<MibSPI2 RAM*/
RAMTYPE_MIBSPI4_RAM = 0x00080000u,/**<MibSPI4 RAM*/

Some diagnostic tests in SDL can not be run in user mode. 

HI Wang,

I have checked the controller version and details. it is TMS570LC43x for reference, i am attaching image also.

sl_types.h:

RAMTYPE_MIBSPI2_RAM = 0x00040000u,/**<MibSPI2 RAM*/            <-- Already Defined 
RAMTYPE_MIBSPI4_RAM = 0x00080000u,/**<MibSPI4 RAM*/             <-- Already Defined 

Important: 

1. which test cases we need to run in supervisor mode (0x13) and which we can run system mode (0x1F)? any document available please let me know?

2. where we can change the mode from supervisor mode (0x13) to system mode (0x1F)? so we can initialize RTOS scheduler properly. otherwise code will never activate scheduler? please support. 

Thanks & Regard 

Pankaj Verma

Pankaj Verma said:

1. which test cases we need to run in supervisor mode (0x13) and which we can run system mode (0x1F)? any document available please let me know?

If the selftest API needs to write WP bit field, you have to switch MCU to privilege mode (non-user mode) before calling this API.

for example:

Pankaj Verma said:

2. where we can change the mode from supervisor mode (0x13) to system mode (0x1F)? so we can initialize RTOS scheduler properly. otherwise code will never activate scheduler? please support. 

FreeRTOS tasks can be created to run in either Privileged mode or Unprivileged mode. A privileged task has access to the entire memory map, can be created using either the xTaskCreate() or xTaskCreateRestricted() API function. An unprivileged task only has access to its stack, and can only be created using the xTaskCreateRestricted() API.

A Privileged mode task can call portSWITCH_TO_USER_MODE() to set itself into Unprivileged mode. A task that is running in Unprivileged mode cannot set itself into Privileged mode.

Both supervisor mode (0x13) to system mode (0x1F) are privileged mode.