TMS570LC4357: Problems with SPI2 Chip Select Bits CSNR and MIBSPI2NCS[0]

Max Wittekind

Part Number: TMS570LC4357

Hi experts,

we are experiencing a slight Problem with the CSNR bits of the SPI2 Modul.

We are configuring pin N3 as MIBSPI2NCS[0] and according to table 28-25 in the Technical Reference CSNR shoudl be 0x1. This does not work.
However setting CSNR to 0x2, which should be Chip Select 1 does work.

This is what we do before writing the SPIDAT1 register:

    data |= ((uint32_t) 1U << 26);
    
    data |= (uint32_t)((uint32_t)0x2 << 16);  // Set Chipselect

    data |= (uint32_t) txData;
    
    SPI->DAT1 = data

Could you check on you end, if the CSNR = 0x2 seletcs pin N3?

Thank you and best regards,
Max

over 2 years ago

+1 jagadish gundavarapu over 2 years ago

TI__Guru 69891 points

Hi Max,

Actually, to activate CS[0] you should write 0xFE to CSNR.

This is because, it's all depending on SPIDEF register.

The default value of the CDEF is 0xFF right, that means chip select pins will act like active low signals and they are set to the 1 when no transfer is going on between master and slave, so to activate CS0 to low while transferring we should write 0xFE to the CSNR.

Similarly, if you write CDEF to the 0x00 then that means chip select pins will act like active high signals and they are set to the 0 when no transfer is going on between master and slave, so in this case to activate CS0 to high while transferring we should write 0x01 to the CSNR.

For more details refer below threads:

(+) TMDXRM57LHDK: Understanding CSNR in SPI1 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

(+) TMS570LS3137: CS pin is not driven when SPI4NCS[0] is configured as SPI Mode - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

(+) TMS570LS1224: Issue of SPI communicaton between TMS570LS12x launchpad and TMDS570LS31HDK - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Thanks & regards,
Jagadish.