Hello TI
I have put my own linker file below. I try to restrict the L2_RAM_BANK0 section to 1MB. And the rest of 1MB is the to be considered for other purposes. There is slight difference with some section in MCAL examples and TRM documentation. Could you please provide that, our linker scrip is correct?
/* This is the stack that is used by code running within main()
* In case of NORTOS,
* - This means all the code outside of ISR uses this stack
* In case of FreeRTOS
* - This means all the code until vTaskStartScheduler() is called in main()
* uses this stack.
* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
*/
--stack_size=16384
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
* This is also the heap used by pvPortMalloc in FreeRTOS
*/
--heap_size=512
--retain="*(.vectors)"
-emain /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
/* This is the size of stack when R5 is in IRQ mode
* In NORTOS,
* - Here interrupt nesting is disabled as of now
* - This is the stack used by ISRs registered as type IRQ
* In FreeRTOS,
* - Here interrupt nesting is enabled
* - This is stack that is used initally when a IRQ is received
* - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
* - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
*/
__CORE0_IRQ_STACK_SIZE = 4096;
/* This is the size of stack when R5 is in IRQ mode
* - In both NORTOS and FreeRTOS nesting is disabled for FIQ
*/
__CORE0_FIQ_STACK_SIZE = 256;
__CORE0_SVC_STACK_SIZE = 8192; /* This is the size of stack when R5 is in SVC mode */
__CORE0_ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */
__CORE0_UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */
/*core 1 stack sizes*/
__CORE1_STACK_SIZE = 256;
__CORE1_IRQ_STACK_SIZE = 4096;
__CORE1_FIQ_STACK_SIZE = 256;
__CORE1_SVC_STACK_SIZE = 8192;
__CORE1_ABORT_STACK_SIZE = 256;
__CORE1_UNDEFINED_STACK_SIZE = 256;
MEMORY
{
PAGE 0:
RESET_VECTORS (X) : ORIGIN = 0x00000000 , LENGTH = 0x100
/*check TCMA_RAM technical reference manual page 35, core 00 and core 01*/
TCMA_RAM (RX) : ORIGIN = 0x00000100 , LENGTH = 0x00003F00
TCMB_RAM (RW) : ORIGIN = 0x00080000 , LENGTH = 0x00008000
/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
L2_RAM_BANK0 (RW) : origin=0x70040000 length=0x100000
CPPI_DESC (RW) : origin=0x70180000 length=0x00004000
/* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
* other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
*/
FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000
/* shared memories that are used by RTOS/NORTOS cores */
/* On R5F,
* - make sure there is a MPU entry which maps below regions as non-cache
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x00004000
LOG_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x00004000
/* MSS mailbox memory is used as shared memory, we dont use bottom 32*12 bytes, since its used as SW queue by ipc_notify */
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x72000000, LENGTH = 0x3E80
L3_RAM (RW) : origin=0x88000000 length=0x00300000
HWA_RAM (RW) : origin=0x28000000 length=0x00020000
PAGE 1:
L3_RAM (RW) : origin=0x88000000 length=0x00300000
}
--define=MCAL_CODE1=L2_RAM_BANK0
--define=MCAL_CODE2=L2_RAM_BANK0
--define=MCAL_DATA=L2_RAM_BANK0
--define=MCAL_BSS=L2_RAM_BANK0
--define=MCAL_NOINIT=L2_RAM_BANK0
--define=MCAL_CONST=L2_RAM_BANK0
--define FILL_PATTERN=0xFEAA55EF
--define FILL_LENGTH=0x100
SECTIONS
{
/* This has the R5F entry point and vector table, this MUST be at 0x0 */
.vectors : {} palign(8) > RESET_VECTORS
.startup : {} palign(8) > TCMA_RAM
.systcmsysvimRam : > TCMA_RAM
/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
* i.e this cannot be placed in DDR
*/
GROUP {
.text.hwi: palign(8)
/*.text.startup: palign(8) // Harbas A. for MCAL*/
.text.cache: palign(8)
.text.mpu: palign(8)
.text.boot: palign(8)
.text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
} > TCMA_RAM
/* TEXT SECTION - Executable Code */
.text : > MCAL_CODE1, fill=FILL_PATTERN
{
.=align(4);
__linker_text_start = .;
. += FILL_LENGTH;
*(.text)
.=align(4);
. += FILL_LENGTH;
__linker_text_end = .;
}
/* CONST SECTION - Initialized Global Variables */
.rodata : load > MCAL_CONST, fill=FILL_PATTERN
{
.=align(4);
__linker_const_start = .;
. += FILL_LENGTH;
*(.rodata)
.=align(4);
. += FILL_LENGTH;
__linker_const_end = .;
}
/* DATA SECTION - Initialized Data */
.data : load > MCAL_DATA, fill=FILL_PATTERN
{
.=align(4);
__linker_data_start = .;
. += FILL_LENGTH;
*(.data)
.=align(4);
. += FILL_LENGTH;
__linker_data_end = .;
}
/* BSS SECTION - Contains Uninitialized Global variables */
.bss : load > MCAL_BSS, fill=FILL_PATTERN
RUN_START(__BSS_START)
RUN_END(__BSS_END)
{
.=align(4);
__linker_bss_start = .;
. += FILL_LENGTH;
*(.bss)
.=align(4);
. += FILL_LENGTH;
__linker_bss_end = .;
}
/* CINIT SECTION - Tables which initializes global variables */
.cinit : load > MCAL_DATA
/* STACK - System Stack */
.stack : load > MCAL_DATA, fill=FILL_PATTERN
/* SYSMEM - Heap Memory */
.sysmem : load > MCAL_DATA
/* This is where the stacks for Core0 R5F modes go */
GROUP {
.core0irqstack: {. = . + __CORE0_IRQ_STACK_SIZE;} align(8)
RUN_START(__CORE0_IRQ_STACK_START)
RUN_END(__CORE0_IRQ_STACK_END)
.core0fiqstack: {. = . + __CORE0_FIQ_STACK_SIZE;} align(8)
RUN_START(__CORE0_FIQ_STACK_START)
RUN_END(__CORE0_FIQ_STACK_END)
.core0svcstack: {. = . + __CORE0_SVC_STACK_SIZE;} align(8)
RUN_START(__CORE0_SVC_STACK_START)
RUN_END(__CORE0_SVC_STACK_END)
.core0abortstack: {. = . + __CORE0_ABORT_STACK_SIZE;} align(8)
RUN_START(__CORE0_ABORT_STACK_START)
RUN_END(__CORE0_ABORT_STACK_END)
.core0undefinedstack: {. = . + __CORE0_UNDEFINED_STACK_SIZE;} align(8)
RUN_START(__CORE0_UNDEFINED_STACK_START)
RUN_END(__CORE0_UNDEFINED_STACK_END)
} > MCAL_DATA
/* This is where the stacks for Core 1 modes go */
GROUP {
.core1stack: {. = . + __CORE1_STACK_SIZE;} align(8)
RUN_START(__CORE1_STACK_START)
RUN_END(__CORE1_STACK_END)
.core1irqstack: {. = . + __CORE1_IRQ_STACK_SIZE;} align(8)
RUN_START(__CORE1_IRQ_STACK_START)
RUN_END(__CORE1_IRQ_STACK_END)
.core1fiqstack: {. = . + __CORE1_FIQ_STACK_SIZE;} align(8)
RUN_START(__CORE1_FIQ_STACK_START)
RUN_END(__CORE1_FIQ_STACK_END)
.core1svcstack: {. = . + __CORE1_SVC_STACK_SIZE;} align(8)
RUN_START(__CORE1_SVC_STACK_START)
RUN_END(__CORE1_SVC_STACK_END)
.core1abortstack: {. = . + __CORE1_ABORT_STACK_SIZE;} align(8)
RUN_START(__CORE1_ABORT_STACK_START)
RUN_END(__CORE1_ABORT_STACK_END)
.core1undefinedstack: {. = . + __CORE1_UNDEFINED_STACK_SIZE;} align(8)
RUN_START(__CORE1_UNDEFINED_STACK_START)
RUN_END(__CORE1_UNDEFINED_STACK_END)
} > MCAL_DATA
/* MCPI Log Buffer */
.MCPILogBuffer : load > MCAL_DATA
McalTextSection : fill=FILL_PATTERN, palign(8) load > MCAL_CODE1
{
.=align(8);
__linker_dio_text_start = .;
. += FILL_LENGTH;
*(DIO_TEXT_SECTION)
*(DIO_ISR_TEXT_SECTION)
*(DIO_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_dio_text_end = .;
.=align(8);
__linker_gpt_text_start = .;
. += FILL_LENGTH;
*(GPT_TEXT_SECTION)
*(GPT_ISR_TEXT_SECTION)
*(GPT_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_gpt_text_end = .;
.=align(8);
__linker_mcu_text_start = .;
. += FILL_LENGTH;
*(MCU_TEXT_SECTION)
*(MCU_ISR_TEXT_SECTION)
*(MCU_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_mcu_text_end = .;
.=align(8);
__linker_port_text_start = .;
. += FILL_LENGTH;
*(PORT_TEXT_SECTION)
*(PORT_ISR_TEXT_SECTION)
*(PORT_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_port_text_end = .;
.=align(8);
__linker_wdg_text_start = .;
. += FILL_LENGTH;
*(WDG_TEXT_SECTION)
*(WDG_ISR_TEXT_SECTION)
*(WDG_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_wdg_text_end = .;
.=align(8);
__linker_spi_text_start = .;
. += FILL_LENGTH;
*(SPI_TEXT_SECTION)
*(SPI_ISR_TEXT_SECTION)
*(SPI_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_spi_text_end = .;
.=align(8);
__linker_can_text_start = .;
. += FILL_LENGTH;
*(CAN_TEXT_SECTION)
*(CAN_ISR_TEXT_SECTION)
*(CAN_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_can_text_end = .;
.=align(8);
__linker_pwm_text_start = .;
. += FILL_LENGTH;
*(PWM_TEXT_SECTION)
*(PWM_ISR_TEXT_SECTION)
*(PWM_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_pwm_text_end = .;
.=align(8);
__linker_icu_text_start = .;
. += FILL_LENGTH;
*(ICU_TEXT_SECTION)
*(ICU_ISR_TEXT_SECTION)
*(ICU_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_icu_text_end = .;
.=align(8);
__linker_adc_text_start = .;
. += FILL_LENGTH;
*(ADC_TEXT_SECTION)
*(ADC_ISR_TEXT_SECTION)
*(ADC_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_adc_text_end = .;
.=align(8);
__linker_ipc_text_start = .;
. += FILL_LENGTH;
*(IPC_TEXT_SECTION)
*(IPC_ISR_TEXT_SECTION)
*(IPC_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_ipc_text_end = .;
.=align(8);
__linker_eth_text_start = .;
. += FILL_LENGTH;
*(ETH_TEXT_SECTION)
*(ETH_ISR_TEXT_SECTION)
*(ETH_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_eth_text_end = .;
.=align(8);
__linker_ethtrcv_text_start = .;
. += FILL_LENGTH;
*(ETHTRCV_TEXT_SECTION)
*(ETHTRCV_ISR_TEXT_SECTION)
*(ETHTRCV_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_ethtrcv_text_end = .;
.=align(4);
__linker_uart_text_start = .;
. += FILL_LENGTH;
*(UART_TEXT_SECTION)
*(UART_ISR_TEXT_SECTION)
*(UART_CALLOUT_TEXT_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_uart_text_end = .;
.=align(8);
__linker_fls_text_start = .;
. += FILL_LENGTH;
*(FLS_TEXT_SECTION)
*(FLS_ISR_TEXT_SECTION)
*(FLS_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_fls_text_end = .;
.=align(8);
__linker_dma_text_start = .;
. += FILL_LENGTH;
*(CDD_DMA_TEXT_SECTION)
*(CDD_DMA_TEXT_SECTION)
*(CDD_DMA_CALLOUT_TEXT_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_dma_text_end = .;
}
McalConstSection : fill=FILL_PATTERN, palign(8) load > MCAL_CONST
{
.=align(8);
__linker_dio_const_start = .;
. += FILL_LENGTH;
*(DIO_CONST_UNSPECIFIED_SECTION)
*(DIO_CONST_32_SECTION)
*(DIO_CONST_16_SECTION)
*(DIO_CONST_8_SECTION)
*(DIO_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_dio_const_end = .;
.=align(8);
__linker_gpt_const_start = .;
. += FILL_LENGTH;
*(GPT_CONST_UNSPECIFIED_SECTION)
*(GPT_CONST_32_SECTION)
*(GPT_CONST_16_SECTION)
*(GPT_CONST_8_SECTION)
*(GPT_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_gpt_const_end = .;
.=align(8);
__linker_mcu_const_start = .;
. += FILL_LENGTH;
*(MCU_CONST_UNSPECIFIED_SECTION)
*(MCU_CONST_32_SECTION)
*(MCU_CONST_16_SECTION)
*(MCU_CONST_8_SECTION)
*(MCU_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_mcu_const_end = .;
.=align(8);
__linker_port_const_start = .;
. += FILL_LENGTH;
*(PORT_CONST_UNSPECIFIED_SECTION)
*(PORT_CONST_32_SECTION)
*(PORT_CONST_16_SECTION)
*(PORT_CONST_8_SECTION)
*(PORT_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_port_const_end = .;
.=align(8);
__linker_wdg_const_start = .;
. += FILL_LENGTH;
*(WDG_CONST_UNSPECIFIED_SECTION)
*(WDG_CONST_32_SECTION)
*(WDG_CONST_16_SECTION)
*(WDG_CONST_8_SECTION)
*(WDG_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_wdg_const_end = .;
.=align(8);
__linker_spi_const_start = .;
. += FILL_LENGTH;
*(SPI_CONST_UNSPECIFIED_SECTION)
*(SPI_CONST_32_SECTION)
*(SPI_CONST_16_SECTION)
*(SPI_CONST_8_SECTION)
*(SPI_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_spi_const_end = .;
.=align(8);
__linker_can_const_start = .;
. += FILL_LENGTH;
*(CAN_CONST_UNSPECIFIED_SECTION)
*(CAN_CONST_32_SECTION)
*(CAN_CONST_16_SECTION)
*(CAN_CONST_8_SECTION)
*(CAN_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_can_const_end = .;
.=align(8);
__linker_pwm_const_start = .;
. += FILL_LENGTH;
*(PWM_CONST_UNSPECIFIED_SECTION)
*(PWM_CONST_32_SECTION)
*(PWM_CONST_16_SECTION)
*(PWM_CONST_8_SECTION)
*(PWM_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_pwm_const_end = .;
.=align(8);
__linker_icu_const_start = .;
. += FILL_LENGTH;
*(ICU_CONST_UNSPECIFIED_SECTION)
*(ICU_CONST_32_SECTION)
*(ICU_CONST_16_SECTION)
*(ICU_CONST_8_SECTION)
*(ICU_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_icu_const_end = .;
.=align(8);
__linker_adc_const_start = .;
. += FILL_LENGTH;
*(ADC_CONST_UNSPECIFIED_SECTION)
*(ADC_CONST_32_SECTION)
*(ADC_CONST_16_SECTION)
*(ADC_CONST_8_SECTION)
*(ADC_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_adc_const_end = .;
.=align(8);
__linker_ipc_const_start = .;
. += FILL_LENGTH;
*(IPC_CONST_32_SECTION)
*(IPC_CONST_UNSPECIFIED_SECTION)
*(IPC_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_ipc_const_end = .;
.=align(8);
__linker_eth_const_start = .;
. += FILL_LENGTH;
*(ETH_CONST_UNSPECIFIED_SECTION)
*(ETH_CONST_32_SECTION)
*(ETH_CONST_16_SECTION)
*(ETH_CONST_8_SECTION)
*(ETH_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_eth_const_end = .;
.=align(8);
__linker_ethtrcv_const_start = .;
. += FILL_LENGTH;
*(ETHTRCV_CONST_UNSPECIFIED_SECTION)
*(ETHTRCV_CONST_32_SECTION)
*(ETHTRCV_CONST_16_SECTION)
*(ETHTRCV_CONST_8_SECTION)
*(ETHTRCV_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_ethtrcv_const_end = .;
.=align(4);
__linker_uart_const_start = .;
. += FILL_LENGTH;
*(UART_CONST_32_SECTION)
*(UART_CONST_UNSPECIFIED_SECTION)
*(UART_CONFIG_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_uart_const_end = .;
.=align(8);
__linker_fls_const_start = .;
. += FILL_LENGTH;
*(FLS_CONST_32_SECTION)
*(FLS_CONST_UNSPECIFIED_SECTION)
*(FLS_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_fls_const_end = .;
.=align(8);
__linker_dma_const_start = .;
. += FILL_LENGTH;
*(CDD_DMA_CONST_UNSPECIFIED_SECTION)
*(CDD_DMA_CONST_32_SECTION)
*(CDD_DMA_CONST_16_SECTION)
*(CDD_DMA_CONST_8_SECTION)
*(CDD_DMA_CONFIG_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_dma_const_end = .;
}
McalInitSection : palign(8) load > MCAL_DATA
{
.=align(8);
__linker_dio_init_start = .;
. += FILL_LENGTH;
*(DIO_DATA_INIT_UNSPECIFIED_SECTION)
*(DIO_DATA_INIT_32_SECTION)
*(DIO_DATA_INIT_16_SECTION)
*(DIO_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_dio_init_end = .;
.=align(8);
__linker_gpt_init_start = .;
. += FILL_LENGTH;
*(GPT_DATA_INIT_UNSPECIFIED_SECTION)
*(GPT_DATA_INIT_32_SECTION)
*(GPT_DATA_INIT_16_SECTION)
*(GPT_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_gpt_init_end = .;
.=align(8);
__linker_mcu_init_start = .;
. += FILL_LENGTH;
*(MCU_DATA_INIT_UNSPECIFIED_SECTION)
*(MCU_DATA_INIT_32_SECTION)
*(MCU_DATA_INIT_16_SECTION)
*(MCU_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_mcu_init_end = .;
.=align(8);
__linker_port_init_start = .;
. += FILL_LENGTH;
*(PORT_DATA_INIT_UNSPECIFIED_SECTION)
*(PORT_DATA_INIT_32_SECTION)
*(PORT_DATA_INIT_16_SECTION)
*(PORT_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_port_init_end = .;
.=align(8);
__linker_wdg_init_start = .;
. += FILL_LENGTH;
*(WDG_DATA_INIT_UNSPECIFIED_SECTION)
*(WDG_DATA_INIT_32_SECTION)
*(WDG_DATA_INIT_16_SECTION)
*(WDG_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_wdg_init_end = .;
.=align(8);
__linker_spi_init_start = .;
. += FILL_LENGTH;
*(SPI_DATA_INIT_UNSPECIFIED_SECTION)
*(SPI_DATA_INIT_32_SECTION)
*(SPI_DATA_INIT_16_SECTION)
*(SPI_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_spi_init_end = .;
.=align(8);
__linker_can_init_start = .;
. += FILL_LENGTH;
*(CAN_DATA_INIT_UNSPECIFIED_SECTION)
*(CAN_DATA_INIT_32_SECTION)
*(CAN_DATA_INIT_16_SECTION)
*(CAN_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_can_init_end = .;
.=align(8);
__linker_pwm_init_start = .;
. += FILL_LENGTH;
*(PWM_DATA_INIT_UNSPECIFIED_SECTION)
*(PWM_DATA_INIT_32_SECTION)
*(PWM_DATA_INIT_16_SECTION)
*(PWM_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_pwm_init_end = .;
.=align(8);
__linker_icu_init_start = .;
. += FILL_LENGTH;
*(ICU_DATA_INIT_UNSPECIFIED_SECTION)
*(ICU_DATA_INIT_32_SECTION)
*(ICU_DATA_INIT_16_SECTION)
*(ICU_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_icu_init_end = .;
.=align(8);
__linker_adc_init_start = .;
. += FILL_LENGTH;
*(ADC_DATA_INIT_UNSPECIFIED_SECTION)
*(ADC_DATA_INIT_32_SECTION)
*(ADC_DATA_INIT_16_SECTION)
*(ADC_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_adc_init_end = .;
.=align(8);
__linker_ipc_init_start = .;
. += FILL_LENGTH;
*(IPC_DATA_INIT_UNSPECIFIED_SECTION)
*(IPC_DATA_INIT_32_SECTION)
*(IPC_DATA_INIT_16_SECTION)
*(IPC_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_ipc_init_end = .;
.=align(8);
__linker_eth_init_start = .;
. += FILL_LENGTH;
*(ETH_DATA_INIT_UNSPECIFIED_SECTION)
*(ETH_DATA_INIT_32_SECTION)
*(ETH_DATA_INIT_16_SECTION)
*(ETH_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_eth_init_end = .;
.=align(8);
__linker_ethtrcv_init_start = .;
. += FILL_LENGTH;
*(ETHTRCV_DATA_INIT_UNSPECIFIED_SECTION)
*(ETHTRCV_DATA_INIT_32_SECTION)
*(ETHTRCV_DATA_INIT_16_SECTION)
*(ETHTRCV_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_ethtrcv_init_end = .;
.=align(4);
__linker_uart_init_start = .;
. += FILL_LENGTH;
*(UART_DATA_INIT_UNSPECIFIED_SECTION)
*(UART_DATA_INIT_32_SECTION)
*(UART_DATA_INIT_16_SECTION)
*(UART_DATA_INIT_8_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_uart_init_end = .;
.=align(8);
__linker_fls_init_start = .;
. += FILL_LENGTH;
*(FLS_DATA_INIT_32_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_fls_init_end = .;
.=align(8);
__linker_dma_init_start = .;
. += FILL_LENGTH;
*(CDD_DMA_DATA_INIT_UNSPECIFIED_SECTION)
*(CDD_DMA_DATA_INIT_32_SECTION)
*(CDD_DMA_DATA_INIT_16_SECTION)
*(CDD_DMA_DATA_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_dma_init_end = .;
}
McalNoInitSection : palign(8) load > MCAL_NOINIT, type = NOINIT
{
.=align(8);
__linker_dio_no_init_start = .;
. += FILL_LENGTH;
*(DIO_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(DIO_DATA_NO_INIT_32_SECTION)
*(DIO_DATA_NO_INIT_16_SECTION)
*(DIO_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_dio_no_init_end = .;
.=align(8);
__linker_gpt_no_init_start = .;
. += FILL_LENGTH;
*(GPT_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(GPT_DATA_NO_INIT_32_SECTION)
*(GPT_DATA_NO_INIT_16_SECTION)
*(GPT_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_gpt_no_init_end = .;
.=align(8);
__linker_mcu_no_init_start = .;
. += FILL_LENGTH;
*(MCU_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(MCU_DATA_NO_INIT_32_SECTION)
*(MCU_DATA_NO_INIT_16_SECTION)
*(MCU_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_mcu_no_init_end = .;
.=align(8);
__linker_port_no_init_start = .;
. += FILL_LENGTH;
*(PORT_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(PORT_DATA_NO_INIT_32_SECTION)
*(PORT_DATA_NO_INIT_16_SECTION)
*(PORT_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_port_no_init_end = .;
.=align(8);
__linker_wdg_no_init_start = .;
. += FILL_LENGTH;
*(WDG_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(WDG_DATA_NO_INIT_32_SECTION)
*(WDG_DATA_NO_INIT_16_SECTION)
*(WDG_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_wdg_no_init_end = .;
.=align(8);
__linker_spi_no_init_start = .;
. += FILL_LENGTH;
*(SPI_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(SPI_DATA_NO_INIT_32_SECTION)
*(SPI_DATA_NO_INIT_16_SECTION)
*(SPI_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_spi_no_init_end = .;
.=align(8);
__linker_can_no_init_start = .;
. += FILL_LENGTH;
*(CAN_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(CAN_DATA_NO_INIT_32_SECTION)
*(CAN_DATA_NO_INIT_16_SECTION)
*(CAN_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_can_no_init_end = .;
.=align(8);
__linker_pwm_no_init_start = .;
. += FILL_LENGTH;
*(PWM_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(PWM_DATA_NO_INIT_32_SECTION)
*(PWM_DATA_NO_INIT_16_SECTION)
*(PWM_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_pwm_no_init_end = .;
.=align(8);
__linker_icu_no_init_start = .;
. += FILL_LENGTH;
*(ICU_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(ICU_DATA_NO_INIT_32_SECTION)
*(ICU_DATA_NO_INIT_16_SECTION)
*(ICU_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_icu_no_init_end = .;
.=align(8);
__linker_adc_no_init_start = .;
. += FILL_LENGTH;
*(ADC_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(ADC_DATA_NO_INIT_32_SECTION)
*(ADC_DATA_NO_INIT_16_SECTION)
*(ADC_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_adc_no_init_end = .;
.=align(8);
__linker_ipc_no_init_start = .;
. += FILL_LENGTH;
*(IPC_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(IPC_DATA_NO_INIT_32_SECTION)
*(IPC_DATA_NO_INIT_16_SECTION)
*(IPC_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_ipc_no_init_end = .;
.=align(8);
__linker_eth_no_init_start = .;
. += FILL_LENGTH;
*(ETH_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(ETH_DATA_NO_INIT_32_SECTION)
*(ETH_DATA_NO_INIT_16_SECTION)
*(ETH_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_eth_no_init_end = .;
.=align(8);
__linker_ethtrcv_no_init_start = .;
. += FILL_LENGTH;
*(ETHTRCV_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(ETHTRCV_DATA_NO_INIT_32_SECTION)
*(ETHTRCV_DATA_NO_INIT_16_SECTION)
*(ETHTRCV_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_ethtrcv_no_init_end = .;
.=align(8);
__linker_dma_no_init_start = .;
. += FILL_LENGTH;
*(CDD_DMA_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(CDD_DMA_DATA_NO_INIT_32_SECTION)
*(CDD_DMA_DATA_NO_INIT_16_SECTION)
*(CDD_DMA_DATA_NO_INIT_8_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_dma_no_init_end = .;
.=align(4);
__linker_uart_no_init_start = .;
. += FILL_LENGTH;
*(UART_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(UART_DATA_NO_INIT_32_SECTION)
*(UART_DATA_NO_INIT_16_SECTION)
*(UART_DATA_NO_INIT_8_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_uart_no_init_end = .;
.=align(8);
__linker_fls_no_init_start = .;
. += FILL_LENGTH;
*(FLS_DATA_NO_INIT_UNSPECIFIED_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_fls_no_init_end = .;
}
.bss.ENET_CPPI_DESC {*(.bss.ENET_CPPI_DESC)} ALIGN (128) > CPPI_DESC
/* Sections needed for C++ projects */
GROUP {
.ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
.init_array: {} palign(8) /* Contains function pointers called before main */
.fini_array: {} palign(8) /* Contains function pointers called after main */
} > MCAL_CODE1
/* General purpose user shared memory, used in some examples */
.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
}
Hier is the location of L2_RAM_BANK0 in the TRM:
Thanks
Best regards
