AM2634-Q1: CSS Studio debugger shows different register mapping details for the ePWM registers than what is mentioned in the datasheet

Hello Ashish,

Apologies for the delayed response here as I have been OOO.

It looks like this is an issue with CCS debugger chip support package register definitions in this case.

Can you confirm which version of CCS and the Sitara MCU Device Support package you are using?

The Register Addendum definition is correct, as TBCTR is a full 32-bit register dedicated to hosting the Time Base Counter value.

The CCS Register View definition is incorrect and actually describes the details of the subsequent TBSTS register.

Please provide us with the relevent version details and I will follow up internally to ensure any possible issue in the Sitara MCU Device Support package are properly addressed.

Best Regards,

Zackary Fleenor

Hi Zack,
I am using Code Composer Studio Version: 12.2.0.00009 

Sitara MCU Device Support package; where can I find this info please?

Both 12.2 and 12.3 are incorrect.

If you look at the file CONTROLSS_G0_EPWM0_CONTROLSS_G0_EPWM0.xml, the RESERVED register was assigned the bitfield rather than skipped, that's why the order was mismatched.

Hi Phoenix and Ashish,

Thanks for bringing this up. We checked and it looks like a mistake was made in our xml generation process, causing the bitfield data for the modules to get offset. We are planning to address this problem in a new version of the chip support package in mid-July. 

In this case, only the name of the bitfield is shown incorrectly while the address of the registers should remain fine. Following the description from the register addendum, you can write your desired value in the full registers' fields rather than writing it down as bitfields values. You can also use the memory browser window to modify the value of registers. In these cases you would be writing to the correct TBCTR bitfield rather than the ones shown since this is what it is actually in the SoC, even if the bitfield in the "Registers" window show something else.

Let me know if this helps or if you need help with anything else related to the issue above. I will update this thread once a fix is added to the support package.

Best,

Daniel

Hi Dan,

In the mean while do you think you can share the patched .xml file which we could use locally; it would help for quicker debugging. Else, we will have to keep comparing the values against the register addendum. 

Hi Ashish,

I do not have the patched .xml yet. Could you please tell me:

• Which EPWM instance you are concerned about
• Which registers you need for evaluation 

Depending on what you need I could provide you with a temporary workaround to facilitate your evaluation by Monday

Best,

Daniel

Hello Dan,

We are concerned about the below registers:
CTLSS_GO_EPWM0::TBCTR (TB Counter Increment)

Hi Ashish,

I have updated file CONTROLSS_G0_EPWM0_CONTRLSS_GO_EPWM0.xml to show the correct bitfields on the above mentioned registers.

CONTROLSS_G0_EPWM0_CONTROLSS_G0_EPWM0.xml

Please follow these instructions:

• Close CCS
• go to <CCS_ROOT>\ccs\ccs_base\common\targetdb\Modules\AM263
• replace current file with the provided one
• reopen CCS and check the registers

You should see that the registers' bitfields are now displayed correctly. Once again, I will update this thread once an official fix is added to the support package.

Best,

Daniel