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TMS570LC4357: Interfacing of SRAM on EMIF

Poornalatha Arulselvan
Prodigy 135 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

In our design, we have interfaced SRAM to EMIF interface of TMS570LC4357.  It is configured using CS3_N.  

On configuring the EMIF for ASYNC2, EMIF clock of 75MHz is seen.  Whereas, the CS3_n, OE_n and WE_n signals are not getting generated from TMS570LC4357.

 We were reviewing all the E2E Forum queries regarding EMIF interface. In one of the Query, it was answered like "nMPUInit( )" to be included before "EMIFASYN2Init( )".  

In the Halcogen Tool, on configuring MPU, it is observed that nMPUInit( ) is not getting generated.

We would like to know, is MPUInit(), mandatory? How to configure the same? 

  • 0
    TI__Guru 73216 points

    Hi Poornalatha,

    I don't know about that work around but first make sure you did below two things correctly.

    1. Make sure the CS3_n pin of the controller you are using is in EMIF pin and you connected right pin to the slave device

    Make sure you connected K17 properly to the slave device.

    2. Make sure you are accessing right address range.

    For example, you should access below highlighted address range to activate the pin

    --

    Thanks & regards,
    Jagadish.