Hi,
I have questions about AM2431 GPMC.
I am planning to use GPMC in Synchronous NOR Flash mode and 32-Bit Address/Data-Multiplexed and GPMCFCLKDIVIDER=0h to communicate with FPGA. And I use GPMC_FCLK_MUX because I want continuous clock output.
Question1: When CSEXTRADELAY=1, is the CSn rising edge timing specification F2 or F3?
Refer to 7.10.5.8.1 GPMC and NOR Flash - Synchronous Mode in the data sheet (www.ti.com/.../am2431), F3 is defined in Table 7-55 as "Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] invalid". F3 is not affected by CSEXTRADELAY=1.
Refer to 12.3.3.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas in User guide (www.ti.com/.../spruim2), There are descriptions of F related to F2, "For nCS rising edge (chip-select deactivated) in reading mode:" and "For nCS rising edge (chip-select deactivated) in writing mode:". F2 is affected by CSEXTRADELAY=1.
When CSEXTRADELAY=1, Is the CSn rising edge (deactivated or invalid) timing specification F2 or F3?
Question2: When Address/Data Multiplexed, is the first transfer of GPMC_AD the address or the 1st data?
Refer to 7.10.5.8.1 GPMC and NOR Flash - Synchronous Mode in the data sheet (www.ti.com/.../am2431), F15 is defined in Table 7-55 as "Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[n:0] transition(11)" and "(11) First transfer only for CLK DIV 1 mode".
Does the "first transfer" mean the address or the first data?
best regards,