This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSPM0G3507: oscillator from xtal

Part Number: MSPM0G3507
Other Parts Discussed in Thread: SYSCONFIG

Hello,

Is there something changed regarding xtal between early samples and serial ones?

I have the same xtal on early samples (A) and new one (B) but when I configure ccs 12.3 on xtal, the pin doesn't oscillate and sw stays stuck in pll synch step

Thanks

BR

Tom

  • Hi Tom,

    It might related to the clock system initialization code. Could you send us the code or you can try to configure with the latest sysconfig v1.16?

    Best regards,

    Cash Hao

  • Hello Cash,

    I posted sysconfig file here:

    https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1241777/mspm0g3507-configuration-changes-pg1-0---pg2-0

    Here is generated clock init:

    SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_CLK_init(void) {
        while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD
             | DL_SYSCTL_CLK_STATUS_HFCLK_GOOD
             | DL_SYSCTL_CLK_STATUS_HSCLK_GOOD
             | DL_SYSCTL_CLK_STATUS_LFOSC_GOOD))
               != (DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD
             | DL_SYSCTL_CLK_STATUS_HFCLK_GOOD
             | DL_SYSCTL_CLK_STATUS_HSCLK_GOOD
             | DL_SYSCTL_CLK_STATUS_LFOSC_GOOD))
        {
            ;
        }
    }




    /*
     * Timer clock configuration to be sourced by LFCLK /  (32768 Hz)
     * timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1)))
     *   992.969696969697 Hz = 32768 Hz / (1 * (32 + 1))
     */
    static const DL_TimerG_ClockConfig gTIMER_0ClockConfig = {
        .clockSel    = DL_TIMER_CLOCK_LFCLK,
        .divideRatio = DL_TIMER_CLOCK_DIVIDE_1,
        .prescale    = 32U,
    };

    Thanks.

    BR. T.

  • Hi Thomas,

    I am going to test it with the configuration CCS v12.3 and sysconfig v1.16. There might be an issue when using clock tree to configure an external crystal and can be solved by not using the clock tree to configure the clock parameter. I will do the test and feedback to you with result. 

    Best regards,

    Cash Hao

  • Hello Cash,

    thanks a lot

    I tried without the clock tree but I end into a conflict on the pins of the xtal for hfclk - i ignored it and the microcontroler starts but with oscilloscope I still don't see any oscillation on xtal

    If you have success please share the full config, please.

    Thanks

    BR. T.

  • Hi Thomas,

    I have done the test and using the sysconfig without clock tree could work. Attached the generated code. 

    /*
     * Copyright (c) 2021, Texas Instruments Incorporated
     * All rights reserved.
     *
     * Redistribution and use in source and binary forms, with or without
     * modification, are permitted provided that the following conditions
     * are met:
     *
     * *  Redistributions of source code must retain the above copyright
     *    notice, this list of conditions and the following disclaimer.
     *
     * *  Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * *  Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     */
    
    /*
     *  ============ ti_msp_dl_config.c =============
     *  Configured MSPM0 DriverLib module definitions
     *
     *  DO NOT EDIT - This file is generated for the MSPM0G350X
     *  by the SysConfig tool.
     */
    
    #include "ti_msp_dl_config.h"
    
    /*
     *  ======== SYSCFG_DL_init ========
     *  Perform any initialization needed before using any board APIs
     */
    SYSCONFIG_WEAK void SYSCFG_DL_init(void)
    {
        SYSCFG_DL_initPower();
        SYSCFG_DL_GPIO_init();
        /* Module-Specific Initializations*/
        SYSCFG_DL_SYSCTL_init();
        SYSCFG_DL_SYSCTL_CLK_init();
    }
    
    SYSCONFIG_WEAK void SYSCFG_DL_initPower(void)
    {
        DL_GPIO_reset(GPIOA);
        DL_GPIO_reset(GPIOB);
    
        DL_GPIO_enablePower(GPIOA);
        DL_GPIO_enablePower(GPIOB);
        delay_cycles(POWER_STARTUP_DELAY);
    }
    
    SYSCONFIG_WEAK void SYSCFG_DL_GPIO_init(void)
    {
    
        /* Configure GPIO/IOMUX for HFXT functionality */
        DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXIN_IOMUX);
        DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXOUT_IOMUX);
    
    }
    
    
    static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig = {
        .inputFreq              = DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ,
    	.rDivClk2x              = 0,
    	.rDivClk1               = 0,
    	.rDivClk0               = 0,
    	.enableCLK2x            = DL_SYSCTL_SYSPLL_CLK2X_DISABLE,
    	.enableCLK1             = DL_SYSCTL_SYSPLL_CLK1_DISABLE,
    	.enableCLK0             = DL_SYSCTL_SYSPLL_CLK0_ENABLE,
    	.sysPLLMCLK             = DL_SYSCTL_SYSPLL_MCLK_CLK0,
    	.sysPLLRef              = DL_SYSCTL_SYSPLL_REF_HFCLK,
    	.qDiv                   = 1,
    	.pDiv                   = DL_SYSCTL_SYSPLL_PDIV_2,
    	
    };
    SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_init(void)
    {
        DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
        DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_32_48_MHZ, 0, false);
    
        /* Check that SYSPLL is disabled before configuration */
        while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF))
               != (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF))
            {
                ;
            }
        DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig);
    	
        DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_SYSPLL);
        DL_SYSCTL_setMCLKDivider(DL_SYSCTL_MCLK_DIVIDER_DISABLE);
        DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_1);
    
    	//Low Power Mode is configured to be SLEEP0
        DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
        DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);
    
    }
    SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_CLK_init(void) {
        while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD
    		 | DL_SYSCTL_CLK_STATUS_HFCLK_GOOD
    		 | DL_SYSCTL_CLK_STATUS_HSCLK_GOOD
    		 | DL_SYSCTL_CLK_STATUS_LFOSC_GOOD))
    	       != (DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD
    		 | DL_SYSCTL_CLK_STATUS_HFCLK_GOOD
    		 | DL_SYSCTL_CLK_STATUS_HSCLK_GOOD
    		 | DL_SYSCTL_CLK_STATUS_LFOSC_GOOD))
    	{
    		;
    	}
    }
    
    
    
    
    ti_msp_dl_config.h

    It seems that when using clock tree to generate the code. Checking the SYSPLL status is before the DL_SYSCTL_setHFCLKSourceHFXTParams() function. And actually, it should check the status after that function. This could cause this issue.

    Best regards,

    Cash Hao

  • Hello Cash,

    thanks a lot

    I let the clock tree but added the  configuration of the crystal at begining of main, seems to work

    Do you see any reasons not to proceed like this as a patch, please?

    Thanks

    BR. T.

    int main(void)
    {
        DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_16_32_MHZ,80, true);
        SYSCFG_DL_init();

  • Hi Thomas,

    I would not recommend to do this. 

    DL_SYSCTL_setHFCLKSourceHFXTParams() function should be called after the GPIO init.

    Best regards,

    Cash Hao

  • Hello Cash,

    ok thanks - will it work or is there a possibility that it works in most of the cases and not work in some other?

    Thanks

    BR. T.

  • Hi,

    The HFXT pins are not configured as HFXT function as default. So it is recommend to configure the HFXT clock after the GPIO init. 

    I am not sure why it works on your chip, but still it is not recommend to do that. 

    Best regards,

    Cash Hao