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EK-TM4C129EXL: SSI EOT Continuous Interrupt

Matthew Constance
Prodigy 80 points
Part Number: EK-TM4C129EXL
Other Parts Discussed in Thread: TM4C129ENCPDT

Hi,

I am having some trouble with the End Of Transmission (EOT) interrupt for SSI1. The interrupt handler is entered as soon as the EOT interrupt is enabled.

I have ensured I have cleared the interrupt flag before enabling the interrupt (as well as in the ISR):

SSIIntClear(SSI1_BASE, SSI_TXEOT);

__nop(); // Allow interrupt flag to clear before re-enabling interrupts
__nop();
__nop();
__nop();
IntEnable(INT_SSI1);

Without going into all the detail, could what I am seeing be related to errata SSI#07 "SSI Transmit Interrupt Status Bit is not Latched"? I think I saw a post with a similar symptom and SSI#07 was the cause, although I can't find the post now.

SSI#07 does not state the EOT interrupt is affected by the silicon issue, I would just like to be sure before I investigate further.

Thank you,

Matthew

  • 0 in reply to Charles Tsai
    Prodigy 80 points

    Hi Charles,

    Thanks for replying so quickly.

    I am partly relieved the errata issue is causing this as I couldn't see what I was doing wrong, but I am also slightly puzzled as the errata does not really describe the issue I am seeing.

    Also, the errata refers to the cases when SSICR1.EOT bit is set and SSICR1.EOT bit is clear. I had not heard of this bit, and in the data sheet (TM4C129ENCPDT, https://www.ti.com/lit/gpn/tm4c129encpdt)  I read that bits 3-5 of the SSICR1 register are reserved, and I see no bit called EOT. The only mention is that this bit has been removed from the data sheet:

    "In the SSI chapter: – Clarified Receive FIFO operation. – Clarified DMA operation. – Removed End of Transmission (EOT) bit 4 from QSSI Control 1 (SSICR1) register"

    Why was it removed? 

    When I look in my CCS registers window I see the EOT bit is clear. I am thinking this should be set if I want the EOT interrupt to work? AlI I am doing to set up the SSI is the following:

    SSIIntDisable(SSI1_BASE, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
    SSIIntClear(SSI1_BASE, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
    IntRegister(INT_SSI1, ssi1_int_handler);
    SSIIntEnable(SSI1_BASE, SSI_TXEOT);
    IntDisable(INT_SSI1);

    SSIEnable(SSI1_BASE);
    SSIDMAEnable(SSI1_BASE, SSI_DMA_RX);

    The ISR starts as (EOT is the only interrupt I intended to use). :

    void ssi1_int_handler(void)
    {
        SSIIntClear(SSI1_BASE, SSI_TXEOT);
        IntDisable(INT_SSI1);

        set_test_pin();

        // etc...

    }

    I looked at another data sheet (TM4C1233) out of curiosity and it states the EOT bit determines when the TXRIS is set, either FIFO half empty or FIFO completely empty.

    Is my initialise code and ISR correct for EOT interrupts please? This is admittedly somewhat academic if the errata issues means this won't work anyway.

    As regards a workaround, I'm not sure the one detailed will help me as I am using a timer DMA channel to write six 16 bit words from RAM into the SSI data register (to sync the SSI clock with a PWM signal to generate a continuous clock). This will expect the FIFO to be empty (it is 8 words deep). Can you think of a suitable workaround method?

    As I am sending the same data length each time, I could start a hardware timer when the SSI TX begins and use its interrupt instead of the SSI interrupt.

    I would welcome your thoughts.

    Regards,

    Matthew 

  • 0 in reply to Matthew Constance
    Prodigy 80 points

    Hi Charles,

    I accidentally marked my previous reply as having resolved the issue, this was a mistake.

    Regards,

    Matthew

  • 0 in reply to Matthew Constance
    TI__Guru**** 191846 points

    Hi Mathew,

    Matthew Constance said:

    Also, the errata refers to the cases when SSICR1.EOT bit is set and SSICR1.EOT bit is clear. I had not heard of this bit, and in the data sheet (TM4C129ENCPDT, https://www.ti.com/lit/gpn/tm4c129encpdt)  I read that bits 3-5 of the SSICR1 register are reserved, and I see no bit called EOT. The only mention is that this bit has been removed from the data sheet:

    "In the SSI chapter: – Clarified Receive FIFO operation. – Clarified DMA operation. – Removed End of Transmission (EOT) bit 4 from QSSI Control 1 (SSICR1) register"

    Why was it removed? 

      I'm reading an internal unpublished datasheet and even it has no EOT bit. Yes, it was perhaps there a one point of time but got removed from a long time ago. I have no history as to why it was removed. 

    Matthew Constance said:
    I looked at another data sheet (TM4C1233) out of curiosity and it states the EOT bit determines when the TXRIS is set, either FIFO half empty or FIFO completely empty.

    TM4C123 uses SSI, not QSSI. I will not reference EOT bit in TM4C123 for TM4C129. It can lead to unknown issue. 

    Matthew Constance said:
    Is my initialise code and ISR correct for EOT interrupts please? This is admittedly somewhat academic if the errata issues means this won't work anyway.

    I don't really see an issue with your code. I will suggest you not reference the EOT bit since it does not exist in the datasheet, although the revision history mentioned about it. It is possible that that bit was there at one point of time but got removed due to bugs that it can manifest when used. I don't really know. I just won't recommend using the bit when it is not there in the latest datasheet. 

    Matthew Constance said:
    As regards a workaround, I'm not sure the one detailed will help me as I am using a timer DMA channel to write six 16 bit words from RAM into the SSI data register (to sync the SSI clock with a PWM signal to generate a continuous clock). This will expect the FIFO to be empty (it is 8 words deep). Can you think of a suitable workaround method?

    Can you try EOTRIS to indicate the end of transmission?

  • 0 in reply to Charles Tsai
    Prodigy 80 points

    Hi Charles,

    Thanks as always for your help with all of this!

    Regards,

    Matthew