AM2634-Q1: Multicore environment questions

Sue A

Part Number: AM2634-Q1
Other Parts Discussed in Thread: SYSCONFIG

Hi TI Expert,

I am running a multicore project and have a few questions. I am not using lock step mode.

1) The interrupts on core 0 are working fine. Similarly, I have set up interrupt on core 1 and it is not working. Is there a difference in setting interrupts on different cores? should the VIM be set up in "split mode"? if yes, how to set this up?

2) how to sync cores in firmware? Is there a mode setting for this?

3) Is there a way to share data between cores? (for example: is it possible to simply create a global variable which can be easily accessed across multiple cores?). what are the different ways to share data between cores and how to set them up?

Thank you in advance!

over 2 years ago

0 Aakash Kedia over 2 years ago

TI__Mastermind 26145 points

Hi Sue A,

Sue A said:
1) The interrupts on core 0 are working fine. Similarly, I have set up interrupt on core 1 and it is not working. Is there a difference in setting interrupts on different cores? should the VIM be set up in "split mode"? if yes, how to set this up?

No, the interrupt setting mechanism for each core is exactly the same. Infact if you check the VIM configuration code, there is no explicit logic to configure it on the basis of the CPUs.

Sue A said:
2) how to sync cores in firmware? Is there a mode setting for this?

What do you mean by "sync" cores ? Do you have a use case which can explain this better ?

Sue A said:
3) Is there a way to share data between cores? (for example: is it possible to simply create a global variable which can be easily accessed across multiple cores?). what are the different ways to share data between cores and how to set them up?

Yes, you can use IPC or Inter-Processor Communication for the same. SDK Example links for the same are here -

Hope it helps.

Best Regards,
Aakash

0 Sue A over 2 years ago in reply to Aakash Kedia

Intellectual 290 points

Hi Aakash,

1) I believe I have set up the interrupt correctly on core_1, however it is still not working. I was wondering if I need to set up VIM in split core capable mode to run interrupts on multiple cores? if yes, could you tell me how to set this mode?

3) Is IPC the only way to share data between cores? What other options are available to share data between cores?

Thank You!

0 Aakash Kedia over 2 years ago in reply to Sue A

TI__Mastermind 26145 points

Hi Sue,

Sue A said:
1) I believe I have set up the interrupt correctly on core_1, however it is still not working. I was wondering if I need to set up VIM in split core capable mode to run interrupts on multiple cores? if yes, could you tell me how to set this mode?

If you enable the LS mode for the cluster, both the CPUs will work with single interrupt controller, controlled via Core 0.

Sue A said:
3) Is IPC the only way to share data between cores? What other options are available to share data between cores?

What type of option are you looking for ? IPC is very memory efficient low latency option with very high throughput. What is your use-case ?

Best Regards,
Aakash

0 Sue A over 2 years ago in reply to Aakash Kedia

Intellectual 290 points

Hi Aakash,

1) As I mentioned I am not using lock step mode. I want to run the cores in dual core mode. In this case, how to enable interrupts in R5FSS0_1. Interrupts in R5FSS0_0 are running fine!

3) If I do not want to use IPC, what other ways I can share data between cores?

Thanks!

0 Sahana H G over 2 years ago in reply to Sue A

TI__Expert 5426 points

Hi Sue,

There is no explicit configuration required to enable interrupts in split mode. In dual core mode, the interrupts need to be set up separately for each core and they should work. Could you please share details on how exactly you're doing this, so that we can let you know if there's a discrepancy.

Thanks,

Sahana

0 Sue A over 2 years ago in reply to Sahana H G

Intellectual 290 points

hi Sahana,

In dual core mode, I am generating an interrupt from EPWM0 module and I have registered the interrupt and also set up the xBAR for interrupt routing on R50_1. Please let me know if I am missing anything?

0 Sahana H G over 2 years ago in reply to Sue A

TI__Expert 5426 points

Hi Sue,

That seems fine, could you also confirm if you're not using the same XBAR output instance on the other core? You could also use the SysConfig tool to setup the XBAR, to avoid conflicts between the cores.

Thanks,

Sahana

0 Sue A over 2 years ago in reply to Sahana H G

Intellectual 290 points

Hi Sahana,

I am using interrupt XBAR instance 1 on R50_0 and interrupt XBAR instance 2 on R50_1. Please let me know if there is anything else I need to check?

0 Sahana H G over 2 years ago in reply to Sue A

TI__Expert 5426 points

Hi Sue,

I see that the interrupt is set up for interrupt XBAR instance 0 (CSLR_R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_0) from your above code. But the XBAR is configured for a different instance?

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AM2634-Q1: Multicore environment questions