RM44L520: The PBIST self-test on RAM overwrites all stack data, so abort is entered after the self-test is complete

Cherry Zhou

Part Number: RM44L520
Other Parts Discussed in Thread: HALCOGEN

Hi team,

When using the diagLib, when the SL_SelfTest_PBIST is called in sys_startup.c to self-test all TCMRAMs, all stack data is overwritten after the self-test completes, so when the function returns, unstacking with POP instructions will enter an abort exception. The customer would like to know if this is an expected behavior. If not, how to fix it?

Could you help check this case? Thanks.

Best Regards,

Cherry

over 2 years ago

+1 jagadish gundavarapu over 2 years ago

TI__Guru 69891 points

Hi Cherry,

This is expected behavior.

The PBIST is usually run on device start-up as it is a destructive test and all contents of the tested SRAM module are overwritten during the test. The SRAM are divided into several groups, and you can place your data and instructions in one SRAM group, and test other SRAM groups.

When you perform PBIST on MCU SRAM, the content in stack area will be lost too. This is why the SRAM pbist test is performed in c_int00() generated by HALCoGen.

If you perform PBIST to SRAM during the startup, you don't need to save the SRAM content to other place since it doesn't contain any useful data (just initialized).

If you perform periodic pbist test on SRAM, you need to save the SRAM content before starting the test.

For more details refer below threads:

(+) RM46L430: Safety Manual states that RAM7A & RAM7B are covered by SL_SelfTest_PBIST, but SL_SelfTest_PBIST cannot be run the TCRAM as running the test corrupts the 'C' runtime system - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

(+) TMS570LC4357: Internal RAM memory test in TMS570LC4357 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Thanks & regards,
Jagadish.

0 Cherry Zhou over 2 years ago in reply to jagadish gundavarapu

TI__Mastermind 22235 points

Hi Jagadish,

Thank you for the support and please let me clarify, this issue occurs when executing SRAM pbist in c_int00 ( ). The sys_startup.c file that is included with TI's diagnostic library is used instead of the halcogen generated file.

As the following code, when calling SL_SelfTest_PBIST, naturally generates a stacking and unstacking operation, which is not consistent with the code generated automatically by halcogen.

void afterSTC(void)
{
    SL_CCMR4F_FailInfo			failInfoCCMR4F;		/* CCMR4 Self Test fail info */
    volatile boolean 			retVal;             /* For function return values */
    SL_PBIST_FailInfo           failInfoPBISTSRAM;  /* PBIST Failure information for TCM RAM */
    SL_SelfTest_Result          failInfoFlash;      /* Flash Self test failure information */
    SL_SelfTest_Result          failInfoTCMRAM;     /* TCM RAM Failure  information */
    SL_PBIST_FailInfo           failInfoPBISTOthers;/* PBIST Failure information for non-TCM memories */
    SL_EFuse_Config             stConfigEFuse;      /* EFuse self test configuration */
    
    ......
    ......
    	retVal = SL_SelfTest_PBIST(	PBIST_EXECUTE,                                          /* Execute PBIST test */
								(PBIST_RAMGROUP_06_ESRAM1 | PBIST_RAMGROUP_21_ESRAM5),  /* On all TCM RAMs */
								PBISTALGO_MARCH13N_RED_1PORT);
    while (TRUE != SL_SelfTest_WaitCompletion_PBIST())
    {
    }
    ......
    ......
}

When debug, an unstacking fault enters abort when the SL_SelfTest_PBIST function returns, but it does enter main normally when release runs at full speed. Why's this?

Thanks and regards,

Cherry

0 jagadish gundavarapu over 2 years ago in reply to Cherry Zhou

TI__Guru 69891 points

Hi Cherry,

I am working on your last issue and will try to provide an update soon.

Thanks & regards,
Jagadish.

0 Cherry Zhou over 2 years ago in reply to jagadish gundavarapu

TI__Mastermind 22235 points

Hi Jagadish,

Thanks and expect your response.

Best,

Cherry

0 QJ Wang over 2 years ago in reply to Cherry Zhou

TI__Guru**** 196776 points

Hi Cherry,

Did you place any instructions and data into the SRAM before executing pbist test? Is the abort Data abort or prefetch abort? What is the fault status in CP15 data fault status register and instruction fault status register?

The different optimization level is used in release mode. Did you find which instruction (disassembly) in pbist selftest function causes the abort?