SCI/LIN multi-buffered mode

Chunyan Li

Other Parts Discussed in Thread: RM44L920, HALCOGEN

Hello, I am using the RM44L920 Hercules microcontroller.

I use the SCI/LIN module as a serial interface to communicate with an external CPU. The SCI/LIN module is configured with the following settings:

Baud rate: 460800
8 data bits, no parity, and one stop bit
Multi-buffered mode with length=0 (response field has 1 byte/character)
Enable interrupt for Framing/Overrun/Parity error, Receive, and Break detect

Unfortunately, after power on, the external CPU sends approximately 200 bytes data with baud rate of 1.8MHz to the RM44L920 microcontroller. As a result, the RM44L920 microcontroller gets stuck at the LIN ISR (linLowLevelInterrupt). The Receive flag (INTVECT1 = 11 / Receive) is consistently asserted after the external CPU sends data to the Hercules microcontroller with 1.8MHz baud rate. However, the bit FE (frame error) in the SCI Flags register is never set to 1, and INTVECT1 is never set to 6 (Frame error), which is expected.

I am wondering why the error interrupt is not being generated (spnu608a, March 2018, Table 26-4 (SCI/LIN Interrupts)). Instead, the Receive flag is always asserted.

When I change the settings of the SCI/LIN module as follows:

Baud rate: 460800
8 data bits, no parity, and one stop bit
Multi-buffered mode with length=0 (response field has 1 byte/character)
Enable interrupt for Receive only

The RM44L920 microcontroller still gets stuck at the LIN ISR (linLowLevelInterrupt) after the external CPU sends data to the Hercules microcontroller with a baud rate of 1.8MHz. The Receive flag (INTVECT1 = 11 / Receive) is consistently asserted. However, as expected, the bit FE (frame error) and OE (overrun error) in the SCI Flags register are set to 1.

By the way, when I set the SCI/LIN module in non multi-buffered mode, everything works well. The microcontroller does not stuck at ISR. Is there anything I missed by using Multi-buffered mode?

over 2 years ago

0 jagadish gundavarapu over 2 years ago

TI__Guru* 76926 points

Hi Chunyan,

We started working on your issue and will provide an update ASAP.

Thanks & regards,
Jagadish.

0 Chunyan Li over 2 years ago in reply to jagadish gundavarapu

Prodigy 30 points

Hi Jagadish,

Do you have any updates on this issue?

Best regards,

Chunyan

0 jagadish gundavarapu over 2 years ago in reply to Chunyan Li

TI__Guru* 76926 points

Hi Chunyan,

I never saw any issues related to this behavior in the past.

May be no one ever tested error behaviors in multi-buffered mode.

If possible, please share your project, if not then I will create another project and do this testing. Please expect some delay for this.

Thanks & regards,
Jagadish.

0 Chunyan Li over 2 years ago in reply to jagadish gundavarapu

Prodigy 30 points

Hi Jagadish,

Unfortunately, I cannot share our project with you as it refers to a security project. However, I can upload some important files that you may need to reproduce the issue (uartQr(*scilinREG) sci/lin at 0xFFF7E400U). Please let me know if you need anything else.

Thank you in advance!

Best regards,

Chunyan

uart.cpp uart.h fixed_size_fifo.h reg_sci.h

Fullscreen 3377.sys_vim.c Download

/** @file sys_vim.c
*   @brief VIM Driver Implementation File
*   @date 11-Dec-2018
*   @version 04.07.01
*
*/

/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/



#include "sys_vim.h"
#include "system.h"
#include "esm.h"

/* USER CODE BEGIN (0) */
/* USER CODE END */

/* Vim Ram Definition */
/** @struct vimRam
*   @brief Vim Ram Definition
*
*   This type is used to access the Vim Ram.
*/
/** @typedef vimRAM_t
*   @brief Vim Ram Type Definition
*
*   This type is used to access the Vim Ram.
*/
typedef volatile struct vimRam
{
    t_isrFuncPTR ISR[VIM_CHANNELS];
} vimRAM_t;

#define vimRAM ((vimRAM_t *)0xFFF82000U)

static const t_isrFuncPTR s_vim_init[128U] =
{
    phantomInterrupt_,
    &esmHighInterrupt,            /* Channel 0 */
    phantomInterrupt_,            /* Channel 1 */
    &rtiCompare0Interrupt,        /* Channel 2 */
    phantomInterrupt_,            /* Channel 3 */
    phantomInterrupt_,            /* Channel 4 */
    phantomInterrupt_,            /* Channel 5 */
    phantomInterrupt_,            /* Channel 6 */
    phantomInterrupt_,            /* Channel 7 */
    phantomInterrupt_,            /* Channel 8 */
    phantomInterrupt_,            /* Channel 9 */
    &het1HighLevelInterrupt,      /* Channel 10 */
    phantomInterrupt_,            /* Channel 11 */
    phantomInterrupt_,            /* Channel 12 */
    phantomInterrupt_,            /* Channel 13 */
    phantomInterrupt_,            /* Channel 14 */
    phantomInterrupt_,            /* Channel 15 */
    phantomInterrupt_,            /* Channel 16 */
    phantomInterrupt_,            /* Channel 17 */
    phantomInterrupt_,            /* Channel 18 */
    phantomInterrupt_,            /* Channel 19 */
    phantomInterrupt_,            /* Channel 20 */
    phantomInterrupt_,            /* Channel 21 */
    phantomInterrupt_,            /* Channel 22 */
    &gioLowLevelInterrupt,        /* Channel 23 */
    phantomInterrupt_,            /* Channel 24 */
    phantomInterrupt_,            /* Channel 25 */
    phantomInterrupt_,            /* Channel 26 */
    &linLowLevelInterrupt,        /* Channel 27 */
    phantomInterrupt_,            /* Channel 28 */
    phantomInterrupt_,            /* Channel 29 */
    phantomInterrupt_,            /* Channel 30 */
    &adc1MagThrCompareInterrupt,  /* Channel 31 */
    phantomInterrupt_,            /* Channel 32 */
    phantomInterrupt_,            /* Channel 33 */
    phantomInterrupt_,            /* Channel 34 */
    phantomInterrupt_,            /* Channel 35 */
    phantomInterrupt_,            /* Channel 36 */
    phantomInterrupt_,            /* Channel 37 */
    phantomInterrupt_,            /* Channel 38 */
    phantomInterrupt_,            /* Channel 39 */
    &dmaBTCAInterrupt,            /* Channel 40 */
    phantomInterrupt_,            /* Channel 41 */
    phantomInterrupt_,            /* Channel 42 */
    phantomInterrupt_,            /* Channel 43 */
    phantomInterrupt_,            /* Channel 44 */
    phantomInterrupt_,            /* Channel 45 */
    phantomInterrupt_,            /* Channel 46 */
    phantomInterrupt_,            /* Channel 47 */
    phantomInterrupt_,            /* Channel 48 */
    phantomInterrupt_,            /* Channel 49 */
    phantomInterrupt_,            /* Channel 50 */
    phantomInterrupt_,            /* Channel 51 */
    phantomInterrupt_,            /* Channel 52 */
    phantomInterrupt_,            /* Channel 53 */
    phantomInterrupt_,            /* Channel 54 */
    phantomInterrupt_,            /* Channel 55 */
    phantomInterrupt_,            /* Channel 56 */
    phantomInterrupt_,            /* Channel 57 */
    phantomInterrupt_,            /* Channel 58 */
    phantomInterrupt_,            /* Channel 59 */
    phantomInterrupt_,            /* Channel 60 */
    phantomInterrupt_,            /* Channel 61 */
    phantomInterrupt_,            /* Channel 62 */
    phantomInterrupt_,            /* Channel 63 */
    phantomInterrupt_,            /* Channel 64 */
    phantomInterrupt_,            /* Channel 65 */
    &i2cInterrupt,                /* Channel 66 */
    phantomInterrupt_,            /* Channel 67 */
    phantomInterrupt_,            /* Channel 68 */
    phantomInterrupt_,            /* Channel 69 */
    phantomInterrupt_,            /* Channel 70 */
    phantomInterrupt_,            /* Channel 71 */
    phantomInterrupt_,            /* Channel 72 */
    phantomInterrupt_,            /* Channel 73 */
    &sciLowLevelInterrupt,        /* Channel 74 */
    phantomInterrupt_,            /* Channel 75 */
    phantomInterrupt_,            /* Channel 76 */
    phantomInterrupt_,            /* Channel 77 */
    phantomInterrupt_,            /* Channel 78 */
    phantomInterrupt_,            /* Channel 79 */
    phantomInterrupt_,            /* Channel 80 */
    phantomInterrupt_,            /* Channel 81 */
    phantomInterrupt_,            /* Channel 82 */
    phantomInterrupt_,            /* Channel 83 */
    phantomInterrupt_,            /* Channel 84 */
    phantomInterrupt_,            /* Channel 85 */
    phantomInterrupt_,            /* Channel 86 */
    phantomInterrupt_,            /* Channel 87 */
    phantomInterrupt_,            /* Channel 88 */
    phantomInterrupt_,            /* Channel 89 */
    phantomInterrupt_,            /* Channel 90 */
    phantomInterrupt_,            /* Channel 91 */
    phantomInterrupt_,            /* Channel 92 */
    phantomInterrupt_,            /* Channel 93 */
    phantomInterrupt_,            /* Channel 94 */
    phantomInterrupt_,            /* Channel 95 */
    phantomInterrupt_,            /* Channel 96 */
    phantomInterrupt_,            /* Channel 97 */
    phantomInterrupt_,            /* Channel 98 */
    phantomInterrupt_,            /* Channel 99 */
    phantomInterrupt_,            /* Channel 100 */
    phantomInterrupt_,            /* Channel 101 */
    phantomInterrupt_,            /* Channel 102 */
    phantomInterrupt_,            /* Channel 103 */
    phantomInterrupt_,            /* Channel 104 */
    phantomInterrupt_,            /* Channel 105 */
    phantomInterrupt_,            /* Channel 106 */
    phantomInterrupt_,            /* Channel 107 */
    phantomInterrupt_,            /* Channel 108 */
    phantomInterrupt_,            /* Channel 109 */
    phantomInterrupt_,            /* Channel 110 */
    phantomInterrupt_,            /* Channel 111 */
    phantomInterrupt_,            /* Channel 112 */
    phantomInterrupt_,            /* Channel 113 */
    phantomInterrupt_,            /* Channel 114 */
    phantomInterrupt_,            /* Channel 115 */
    phantomInterrupt_,            /* Channel 116 */
    phantomInterrupt_,            /* Channel 117 */
    phantomInterrupt_,            /* Channel 118 */
    phantomInterrupt_,            /* Channel 119 */
    phantomInterrupt_,            /* Channel 120 */
    phantomInterrupt_,            /* Channel 121 */
    phantomInterrupt_,            /* Channel 122 */
    phantomInterrupt_,            /* Channel 123 */
    phantomInterrupt_,            /* Channel 124 */
    phantomInterrupt_,            /* Channel 125 */
    phantomInterrupt_,            /* Channel 126 */
};
IRQ
void vimParityErrorHandler(void);

/** @fn void vimInit(void)
*   @brief Initializes VIM module
*
*   This function initializes VIM RAM and registers
*/
/* SourceId : VIM_SourceId_001 */
/* DesignId : VIM_DesignId_001 */
/* Requirements : HL_SR100 */
void vimInit(void)
{
	/* VIM RAM Parity Enable */
	VIM_PARCTL = 0xAU;

	/* Initialize VIM table */
    {
        uint32 i;

        for (i = 0U; i < VIM_CHANNELS; i++)
        {
            vimRAM->ISR[i] = s_vim_init[i];
        }
    }

    /* Set Fall-Back Address Parity Error Register */
	/*SAFETYMCUSW 439 S MR:11.3 <APPROVED> " Need to store the address of a function in a 32 bit register - Advisory as per MISRA" */
    VIM_FBPARERR = (uint32)&vimParityErrorHandler;

    /* set IRQ/FIQ priorities */
    vimREG->FIRQPR0 = (uint32)((uint32)SYS_FIQ << 0U)
                    | (uint32)((uint32)SYS_FIQ << 1U)
                    | (uint32)((uint32)SYS_IRQ << 2U)
                    | (uint32)((uint32)SYS_IRQ << 3U)
                    | (uint32)((uint32)SYS_IRQ << 4U)
                    | (uint32)((uint32)SYS_IRQ << 5U)
                    | (uint32)((uint32)SYS_IRQ << 6U)
                    | (uint32)((uint32)SYS_IRQ << 7U)
                    | (uint32)((uint32)SYS_IRQ << 8U)
                    | (uint32)((uint32)SYS_IRQ << 9U)
                    | (uint32)((uint32)SYS_IRQ << 10U)
                    | (uint32)((uint32)SYS_IRQ << 11U)
                    | (uint32)((uint32)SYS_IRQ << 12U)
                    | (uint32)((uint32)SYS_IRQ << 13U)
                    | (uint32)((uint32)SYS_IRQ << 14U)
                    | (uint32)((uint32)SYS_IRQ << 15U)
                    | (uint32)((uint32)SYS_IRQ << 16U)
                    | (uint32)((uint32)SYS_IRQ << 17U)
                    | (uint32)((uint32)SYS_IRQ << 18U)
                    | (uint32)((uint32)SYS_IRQ << 19U)
                    | (uint32)((uint32)SYS_IRQ << 20U)
                    | (uint32)((uint32)SYS_IRQ << 21U)
                    | (uint32)((uint32)SYS_IRQ << 22U)
                    | (uint32)((uint32)SYS_IRQ << 23U)
                    | (uint32)((uint32)SYS_IRQ << 24U)
                    | (uint32)((uint32)SYS_IRQ << 25U)
                    | (uint32)((uint32)SYS_IRQ << 26U)
                    | (uint32)((uint32)SYS_IRQ << 27U)
                    | (uint32)((uint32)SYS_IRQ << 28U)
                    | (uint32)((uint32)SYS_IRQ << 29U)
                    | (uint32)((uint32)SYS_IRQ << 30U)
                    | (uint32)((uint32)SYS_IRQ << 31U);

    vimREG->FIRQPR1 = (uint32)((uint32)SYS_IRQ << 0U)
                    | (uint32)((uint32)SYS_IRQ << 1U)
                    | (uint32)((uint32)SYS_IRQ << 2U)
                    | (uint32)((uint32)SYS_IRQ << 3U)
                    | (uint32)((uint32)SYS_IRQ << 4U)
                    | (uint32)((uint32)SYS_IRQ << 5U)
                    | (uint32)((uint32)SYS_IRQ << 6U)
                    | (uint32)((uint32)SYS_IRQ << 7U)
                    | (uint32)((uint32)SYS_IRQ << 8U)
                    | (uint32)((uint32)SYS_IRQ << 9U)
                    | (uint32)((uint32)SYS_IRQ << 10U)
                    | (uint32)((uint32)SYS_IRQ << 11U)
                    | (uint32)((uint32)SYS_IRQ << 12U)
                    | (uint32)((uint32)SYS_IRQ << 13U)
                    | (uint32)((uint32)SYS_IRQ << 14U)
                    | (uint32)((uint32)SYS_IRQ << 15U)
                    | (uint32)((uint32)SYS_IRQ << 16U)
                    | (uint32)((uint32)SYS_IRQ << 17U)
                    | (uint32)((uint32)SYS_IRQ << 18U)
                    | (uint32)((uint32)SYS_IRQ << 19U)
                    | (uint32)((uint32)SYS_IRQ << 20U)
                    | (uint32)((uint32)SYS_IRQ << 21U)
                    | (uint32)((uint32)SYS_IRQ << 22U)
                    | (uint32)((uint32)SYS_IRQ << 23U)
                    | (uint32)((uint32)SYS_IRQ << 24U)
                    | (uint32)((uint32)SYS_IRQ << 25U)
                    | (uint32)((uint32)SYS_IRQ << 26U)
                    | (uint32)((uint32)SYS_IRQ << 27U)
                    | (uint32)((uint32)SYS_IRQ << 28U)
                    | (uint32)((uint32)SYS_IRQ << 29U)
                    | (uint32)((uint32)SYS_IRQ << 30U)
                    | (uint32)((uint32)SYS_IRQ << 31U);


    vimREG->FIRQPR2 = (uint32)((uint32)SYS_IRQ << 0U)
                    | (uint32)((uint32)SYS_IRQ << 1U)
                    | (uint32)((uint32)SYS_IRQ << 2U)
                    | (uint32)((uint32)SYS_IRQ << 3U)
                    | (uint32)((uint32)SYS_IRQ << 4U)
                    | (uint32)((uint32)SYS_IRQ << 5U)
                    | (uint32)((uint32)SYS_IRQ << 6U)
                    | (uint32)((uint32)SYS_IRQ << 7U)
                    | (uint32)((uint32)SYS_IRQ << 8U)
                    | (uint32)((uint32)SYS_IRQ << 9U)
                    | (uint32)((uint32)SYS_IRQ << 10U)
                    | (uint32)((uint32)SYS_IRQ << 11U)
                    | (uint32)((uint32)SYS_IRQ << 12U)
                    | (uint32)((uint32)SYS_IRQ << 13U)
                    | (uint32)((uint32)SYS_IRQ << 14U)
                    | (uint32)((uint32)SYS_IRQ << 15U)
                    | (uint32)((uint32)SYS_IRQ << 16U)
                    | (uint32)((uint32)SYS_IRQ << 17U)
                    | (uint32)((uint32)SYS_IRQ << 18U)
                    | (uint32)((uint32)SYS_IRQ << 19U)
                    | (uint32)((uint32)SYS_IRQ << 20U)
                    | (uint32)((uint32)SYS_IRQ << 21U)
                    | (uint32)((uint32)SYS_IRQ << 22U)
                    | (uint32)((uint32)SYS_IRQ << 23U)
                    | (uint32)((uint32)SYS_IRQ << 24U)
                    | (uint32)((uint32)SYS_IRQ << 25U)
                    | (uint32)((uint32)SYS_IRQ << 26U)
                    | (uint32)((uint32)SYS_IRQ << 27U)
                    | (uint32)((uint32)SYS_IRQ << 28U)
                    | (uint32)((uint32)SYS_IRQ << 29U)
                    | (uint32)((uint32)SYS_IRQ << 30U)
                    | (uint32)((uint32)SYS_IRQ << 31U);

    vimREG->FIRQPR3 = (uint32)((uint32)SYS_IRQ << 0U)
                    | (uint32)((uint32)SYS_IRQ << 1U)
                    | (uint32)((uint32)SYS_IRQ << 2U)
                    | (uint32)((uint32)SYS_IRQ << 3U)
                    | (uint32)((uint32)SYS_IRQ << 4U)
                    | (uint32)((uint32)SYS_IRQ << 5U)
                    | (uint32)((uint32)SYS_IRQ << 6U)
                    | (uint32)((uint32)SYS_IRQ << 7U)
                    | (uint32)((uint32)SYS_IRQ << 8U)
                    | (uint32)((uint32)SYS_IRQ << 9U)
                    | (uint32)((uint32)SYS_IRQ << 10U)
                    | (uint32)((uint32)SYS_IRQ << 11U)
                    | (uint32)((uint32)SYS_IRQ << 12U)
                    | (uint32)((uint32)SYS_IRQ << 13U)
                    | (uint32)((uint32)SYS_IRQ << 14U)
                    | (uint32)((uint32)SYS_IRQ << 15U)
                    | (uint32)((uint32)SYS_IRQ << 16U)
                    | (uint32)((uint32)SYS_IRQ << 17U)
                    | (uint32)((uint32)SYS_IRQ << 18U)
                    | (uint32)((uint32)SYS_IRQ << 19U)
                    | (uint32)((uint32)SYS_IRQ << 20U)
                    | (uint32)((uint32)SYS_IRQ << 21U)
                    | (uint32)((uint32)SYS_IRQ << 22U)
                    | (uint32)((uint32)SYS_IRQ << 23U)
                    | (uint32)((uint32)SYS_IRQ << 24U)
                    | (uint32)((uint32)SYS_IRQ << 25U)
                    | (uint32)((uint32)SYS_IRQ << 26U)
                    | (uint32)((uint32)SYS_IRQ << 27U)
                    | (uint32)((uint32)SYS_IRQ << 28U)
                    | (uint32)((uint32)SYS_IRQ << 29U)
                    | (uint32)((uint32)SYS_IRQ << 30U)
                    | (uint32)((uint32)SYS_IRQ << 31U);


    /* enable interrupts */
    vimREG->REQMASKSET0 = (uint32)((uint32)1U << 0U)
                        | (uint32)((uint32)0U << 1U)
                        | (uint32)((uint32)1U << 2U)
                        | (uint32)((uint32)0U << 3U)
                        | (uint32)((uint32)0U << 4U)
                        | (uint32)((uint32)0U << 5U)
                        | (uint32)((uint32)0U << 6U)
                        | (uint32)((uint32)0U << 7U)
                        | (uint32)((uint32)0U << 8U)
                        | (uint32)((uint32)0U << 9U)
                        | (uint32)((uint32)1U << 10U)
                        | (uint32)((uint32)0U << 11U)
                        | (uint32)((uint32)0U << 12U)
                        | (uint32)((uint32)0U << 13U)
                        | (uint32)((uint32)0U << 14U)
                        | (uint32)((uint32)0U << 15U)
                        | (uint32)((uint32)0U << 16U)
                        | (uint32)((uint32)0U << 17U)
                        | (uint32)((uint32)0U << 18U)
                        | (uint32)((uint32)0U << 19U)
                        | (uint32)((uint32)0U << 20U)
                        | (uint32)((uint32)0U << 21U)
                        | (uint32)((uint32)0U << 22U)
                        | (uint32)((uint32)1U << 23U)
                        | (uint32)((uint32)0U << 24U)
                        | (uint32)((uint32)0U << 25U)
                        | (uint32)((uint32)0U << 26U)
                        | (uint32)((uint32)1U << 27U)
                        | (uint32)((uint32)0U << 28U)
                        | (uint32)((uint32)0U << 29U)
                        | (uint32)((uint32)0U << 30U)
                        | (uint32)((uint32)1U << 31U);

    vimREG->REQMASKSET1 = (uint32)((uint32)0U << 0U)
                        | (uint32)((uint32)0U << 1U)
                        | (uint32)((uint32)0U << 2U)
                        | (uint32)((uint32)0U << 3U)
                        | (uint32)((uint32)0U << 4U)
                        | (uint32)((uint32)0U << 5U)
                        | (uint32)((uint32)0U << 6U)
                        | (uint32)((uint32)0U << 7U)
                        | (uint32)((uint32)1U << 8U)
                        | (uint32)((uint32)0U << 9U)
                        | (uint32)((uint32)0U << 10U)
                        | (uint32)((uint32)0U << 11U)
                        | (uint32)((uint32)0U << 12U)
                        | (uint32)((uint32)0U << 13U)
                        | (uint32)((uint32)0U << 14U)
                        | (uint32)((uint32)0U << 15U)
                        | (uint32)((uint32)0U << 16U)
                        | (uint32)((uint32)0U << 17U)
                        | (uint32)((uint32)0U << 18U)
                        | (uint32)((uint32)0U << 19U)
                        | (uint32)((uint32)0U << 20U)
                        | (uint32)((uint32)0U << 21U)
                        | (uint32)((uint32)0U << 22U)
                        | (uint32)((uint32)0U << 23U)
                        | (uint32)((uint32)0U << 24U)
                        | (uint32)((uint32)0U << 25U)
                        | (uint32)((uint32)0U << 26U)
                        | (uint32)((uint32)0U << 27U)
                        | (uint32)((uint32)0U << 28U)
                        | (uint32)((uint32)0U << 29U)
                        | (uint32)((uint32)0U << 30U)
                        | (uint32)((uint32)0U << 31U);

    vimREG->REQMASKSET2 = (uint32)((uint32)0U << 0U)
                        | (uint32)((uint32)0U << 1U)
                        | (uint32)((uint32)1U << 2U)
                        | (uint32)((uint32)0U << 3U)
                        | (uint32)((uint32)0U << 4U)
                        | (uint32)((uint32)0U << 5U)
                        | (uint32)((uint32)0U << 6U)
                        | (uint32)((uint32)0U << 7U)
                        | (uint32)((uint32)0U << 8U)
                        | (uint32)((uint32)0U << 9U)
                        | (uint32)((uint32)1U << 10U)
                        | (uint32)((uint32)0U << 11U)
                        | (uint32)((uint32)0U << 12U)
                        | (uint32)((uint32)0U << 13U)
                        | (uint32)((uint32)0U << 14U)
                        | (uint32)((uint32)0U << 15U)
                        | (uint32)((uint32)0U << 16U)
                        | (uint32)((uint32)0U << 17U)
                        | (uint32)((uint32)0U << 18U)
                        | (uint32)((uint32)0U << 19U)
                        | (uint32)((uint32)0U << 20U)
                        | (uint32)((uint32)0U << 21U)
                        | (uint32)((uint32)0U << 22U)
                        | (uint32)((uint32)0U << 23U)
                        | (uint32)((uint32)0U << 24U)
                        | (uint32)((uint32)0U << 25U)
                        | (uint32)((uint32)0U << 26U)
                        | (uint32)((uint32)0U << 27U)
                        | (uint32)((uint32)0U << 28U)
                        | (uint32)((uint32)0U << 29U)
                        | (uint32)((uint32)0U << 30U)
                        | (uint32)((uint32)0U << 31U);

    vimREG->REQMASKSET3 = (uint32)((uint32)0U << 0U)
                        | (uint32)((uint32)0U << 1U)
                        | (uint32)((uint32)0U << 2U)
                        | (uint32)((uint32)0U << 3U)
                        | (uint32)((uint32)0U << 4U)
                        | (uint32)((uint32)0U << 5U)
                        | (uint32)((uint32)0U << 6U)
                        | (uint32)((uint32)0U << 7U)
                        | (uint32)((uint32)0U << 8U)
                        | (uint32)((uint32)0U << 9U)
                        | (uint32)((uint32)0U << 10U)
                        | (uint32)((uint32)0U << 11U)
                        | (uint32)((uint32)0U << 12U)
                        | (uint32)((uint32)0U << 13U)
                        | (uint32)((uint32)0U << 14U)
                        | (uint32)((uint32)0U << 15U)
                        | (uint32)((uint32)0U << 16U)
                        | (uint32)((uint32)0U << 17U)
                        | (uint32)((uint32)0U << 18U)
                        | (uint32)((uint32)0U << 19U)
                        | (uint32)((uint32)0U << 20U)
                        | (uint32)((uint32)0U << 21U)
                        | (uint32)((uint32)0U << 22U)
                        | (uint32)((uint32)0U << 23U)
                        | (uint32)((uint32)0U << 24U)
                        | (uint32)((uint32)0U << 25U)
                        | (uint32)((uint32)0U << 26U)
                        | (uint32)((uint32)0U << 27U)
                        | (uint32)((uint32)0U << 28U)
                        | (uint32)((uint32)0U << 29U)
                        | (uint32)((uint32)0U << 30U)
                        | (uint32)((uint32)0U << 31U);

    /* Set Capture event sources */
	vimREG->CAPEVT = ((uint32)((uint32)0U << 0U)
	                 |(uint32)((uint32)0U << 16U));
}


IRQ

/* SourceId : VIM_SourceId_006 */
/* DesignId : VIM_DesignId_006 */
/* Requirements : HL_SR105 */
void vimParityErrorHandler(void)
{
    uint32 vec;

    /* Identify the corrupted address */
    uint32 error_addr = VIM_ADDERR;

    /* Identify the channel number */
    uint32 error_channel = ((error_addr & 0x1FFU) >> 2U);

    /* Correct the corrupted location */
    vimRAM->ISR[error_channel] = s_vim_init[error_channel];

    /* Clear Parity Error Flag */
    VIM_PARFLG = 1U;

    /* Disable and enable the highest priority pending channel */
    if (vimREG->FIQINDEX != 0U)
    {
        vec = vimREG->FIQINDEX - 1U;
    }
    else
    {
	   /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Read 32 bit volatile register" */
        vec = vimREG->IRQINDEX - 1U;
    }
    if(vec == 0U)
    {
        vimREG->INTREQ0 = 1U;
	    vec = esmREG->IOFFHR - 1U;

        if (vec < 32U)
        {
            esmREG->SR1[0U] = (uint32)1U << vec;
            esmGroup1Notification(vec);
        }
        else if (vec < 64U)
        {
            esmREG->SR1[1U] = (uint32)1U << (vec-32U);
            esmGroup2Notification(vec-32U);
        }
        else if (vec < 96U)
        {
            esmREG->SR4[0U] = (uint32)1U << (vec-64U);
            esmGroup1Notification(vec-32U);
        }
        else
        {
            esmREG->SR4[1U] = (uint32)1U << (vec-96U);
            esmGroup2Notification(vec-64U);
        }
    }
    else if (vec < 32U)
    {
        vimREG->REQMASKCLR0 = (uint32)1U << vec;
        vimREG->REQMASKSET0 = (uint32)1U << vec;
    }
    else if (vec < 64U)
    {
        vimREG->REQMASKCLR1 = (uint32)1U << (vec-32U);
        vimREG->REQMASKSET1 = (uint32)1U << (vec-32U);
    }
    else if(vec < 96U)
    {
        vimREG->REQMASKCLR2 = (uint32)1U << (vec-64U);
        vimREG->REQMASKSET2 = (uint32)1U << (vec-64U);
    }
	else
	{
	    vimREG->REQMASKCLR3 = (uint32)1U << (vec-96U);
        vimREG->REQMASKSET3 = (uint32)1U << (vec-96U);
	}
}

Fullscreen 7271.sys_startup.c Download

/** @file sys_startup.c
*   @brief Startup Source File
*   @date 11-Dec-2018
*   @version 04.07.01
*
*   This file contains:
*   - Include Files
*   - Type Definitions
*   - External Functions
*   - VIM RAM Setup
*   - Startup Routine
*   .
*   which are relevant for the Startup.
*/

/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/


/* USER CODE BEGIN (0) */
/* USER CODE END */


/* Include Files */

#include "sys_common.h"
#include "system.h"
#include "sys_vim.h"
#include "sys_core.h"
#include "sys_selftest.h"
#include "esm.h"
#include "reg_mibspi.h"

#include "errata_SSWF021_45.h"
/* USER CODE BEGIN (1) */
/* USER CODE END */


/* USER CODE BEGIN (2) */
/* USER CODE END */


/* External Functions */

extern void __cmain(void);

void afterSTC(void);

/* USER CODE BEGIN (3) */
/* USER CODE END */
void handlePLLLockFail(void);
/* Startup Routine */
void _c_int00(void);
#define PLL_RETRIES 5U
/* USER CODE BEGIN (4) */
/* USER CODE END */

/* Note: stackless keyword is supported since compiler version 6.20.1 */
__stackless
__arm

/* SourceId : STARTUP_SourceId_001 */
/* DesignId : STARTUP_DesignId_001 */
/* Requirements : HL_SR508 */
void _c_int00(void)
{
/* USER CODE BEGIN (5) */
/* USER CODE END */

    /* Initialize Core Registers to avoid CCM Error */
    _coreInitRegisters_();

/* USER CODE BEGIN (6) */
/* USER CODE END */

    /* Initialize Stack Pointers */
    _coreInitStackPointer_();

/* USER CODE BEGIN (7) */
/* USER CODE END */

    /* Enable CPU Event Export */
    /* This allows the CPU to signal any single-bit or double-bit errors detected
     * by its ECC logic for accesses to program flash or data RAM.
     */
    _coreEnableEventBusExport_();

/* USER CODE BEGIN (11) */
/* USER CODE END */

        /* Workaround for Errata CORTEXR4 66 */
        _errata_CORTEXR4_66_();

        /* Workaround for Errata CORTEXR4 57 */
        _errata_CORTEXR4_57_();

    /* Reset handler: the following instructions read from the system exception status register
     * to identify the cause of the CPU reset.
     */

    /* check for power-on reset condition */
    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
    if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
    {
/* USER CODE BEGIN (12) */
/* USER CODE END */
        /* Add condition to check whether PLL can be started successfully */
        if (_errata_SSWF021_45_pll1(PLL_RETRIES) != 0U)
        {
            /* Put system in a safe state */
			handlePLLLockFail();
        }
        /* clear all reset status flags */
        SYS_EXCEPTION = 0xFFFFU;

/* USER CODE BEGIN (13) */
/* USER CODE END */
/* USER CODE BEGIN (14) */
/* USER CODE END */
/* USER CODE BEGIN (15) */
/* USER CODE END */
      /* continue with normal start-up sequence */
    }
    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
    else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
    {
        /* Reset caused due to oscillator failure.
        Add user code here to handle oscillator failure */

/* USER CODE BEGIN (16) */
/* USER CODE END */
    }
    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
    else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
    {
        /* Reset caused due
         *  1) windowed watchdog violation - Add user code here to handle watchdog violation.
         *  2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
         */
        /* Check the WatchDog Status register */
        if(WATCHDOG_STATUS != 0U)
        {
            /* Add user code here to handle watchdog violation. */
/* USER CODE BEGIN (17) */
/* USER CODE END */

            /* Clear the Watchdog reset flag in Exception Status register */
            SYS_EXCEPTION = WATCHDOG_RESET;

/* USER CODE BEGIN (18) */
/* USER CODE END */
        }
        else
        {
            /* Clear the ICEPICK reset flag in Exception Status register */
            SYS_EXCEPTION = ICEPICK_RESET;
/* USER CODE BEGIN (19) */
/* USER CODE END */
		}
    }
    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
    else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
    {
        /* Reset caused due to CPU reset.
        CPU reset can be caused by CPU self-test completion, or
        by toggling the "CPU RESET" bit of the CPU Reset Control Register. */

/* USER CODE BEGIN (20) */
/* USER CODE END */

        /* clear all reset status flags */
        SYS_EXCEPTION = CPU_RESET;

        /* reset could be caused by stcSelfCheck run or by an actual CPU self-test run */

        /* check if this was an stcSelfCheck run */
        if ((stcREG->STCSCSCR & 0xFU) == 0xAU)
        {
            /* check if the self-test fail bit is set */
            if ((stcREG->STCGSTAT & 0x3U) != 0x3U)
            {
                /* STC self-check has failed */
                stcSelfCheckFail();
            }
            /* STC self-check has passed */
            else
            {
                /* Set self-check mode to the special value 0x09.
                   Default value is 0x05U; setting this register to 0x09U
                   will signal the bootloader to omit initialisations that
                   would disturb the CCM self check to follow after the next reset.

                   Note: The microcontroller only distinguishes the two
                   cases value equal to 0xA or different, for the lower nibble.
                */
                stcREG->STCSCSCR = 0x09U;

                /* clear STC global status flags */
                stcREG->STCGSTAT = 0x3U;

                /* clear ESM group1 channel 27 status flag */
                esmREG->SR1[0U] = 0x08000000U;

                /* Start CPU Self-Test */
                cpuSelfTest(STC_INTERVAL, STC_MAX_TIMEOUT, TRUE);
            }
        }
        /* CPU reset caused by CPU self-test completion */
        else
        {
            /* Set self-check mode back to the default value 0x05.
               This will signal the bootloader to perform normal initialisations.
            */
            stcREG->STCSCSCR = 0x05U;

            if ((stcREG->STCGSTAT & 0x1U) == 0x1U)
            {
                /* Self-Test Fail flag is set */
                if ((stcREG->STCGSTAT & 0x2U) == 0x2U)
                {
                    /* Call CPU self-test failure handler */
                    cpuSelfTestFail();
                }
                /* CPU self-test completed successfully */
                else
                {
                    /* clear STC global status flag */
                    stcREG->STCGSTAT = 0x1U;

                    /* Continue start-up sequence after CPU STC completed */
                    afterSTC();
                }
            }
            /* CPU reset caused by software writing to CPU RESET bit */
            else
            {
                /* Add custom routine here to handle the case where software causes CPU reset */
            }
        }
/* USER CODE BEGIN (21) */
/* USER CODE END */

    }
    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
    else if ((SYS_EXCEPTION & SW_RESET) != 0U)
    {
        /* Reset caused due to software reset.
        Add user code to handle software reset. */

/* USER CODE BEGIN (22) */
/* USER CODE END */
	}
    else
    {
        /* Reset caused by nRST being driven low externally.
        Add user code to handle external reset. */

/* USER CODE BEGIN (23) */
/* USER CODE END */
	}

    /* Check if there were ESM group3 errors during power-up.
     * These could occur during eFuse auto-load or during reads from flash OTP
     * during power-up. Device operation is not reliable and not recommended
     * in this case.
     * An ESM group3 error only drives the nERROR pin low. An external circuit
     * that monitors the nERROR pin must take the appropriate action to ensure that
     * the system is placed in a safe state, as determined by the application.
     */
    if ((esmREG->SR1[2]) != 0U)
    {
/* USER CODE BEGIN (24) */
/* USER CODE END */
    /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
    /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
        for(;;)
        {
        }/* Wait */
/* USER CODE BEGIN (25) */
/* USER CODE END */
    }

/* USER CODE BEGIN (26) */
/* USER CODE END */

    /* Initialize System - Clock, Flash settings with Efuse self check */
    systemInit();

    /* Workaround for Errata PBIST#4 */
    errata_PBIST_4();

    /* Run a diagnostic check on the memory self-test controller.
     * This function chooses a RAM test algorithm and runs it on an on-chip ROM.
     * The memory self-test is expected to fail. The function ensures that the PBIST controller
     * is capable of detecting and indicating a memory self-test failure.
     */
    pbistSelfCheck();

    /* Run PBIST on STC ROM */
    pbistRun((uint32)STC_ROM_PBIST_RAM_GROUP,
             ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
    
    /* Wait for PBIST for STC ROM to be completed */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while(pbistIsTestCompleted() != TRUE)
    { 
    }/* Wait */ 
    
    /* Check if PBIST on STC ROM passed the self-test */
    if( pbistIsTestPassed() != TRUE)
    {
        /* PBIST and STC ROM failed the self-test.
         * Need custom handler to check the memory failure
         * and to take the appropriate next step.
         */
         
        pbistFail();

    }   
	
    /* Disable PBIST clocks and disable memory self-test mode */
    pbistStop();

	/* Run PBIST on PBIST ROM */
    pbistRun((uint32)PBIST_ROM_PBIST_RAM_GROUP,
             ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
    
    /* Wait for PBIST for PBIST ROM to be completed */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while(pbistIsTestCompleted() != TRUE)
    { 
    }/* Wait */ 
    
    /* Check if PBIST ROM passed the self-test */
    if( pbistIsTestPassed() != TRUE)
    {
        /* PBIST and STC ROM failed the self-test.
         * Need custom handler to check the memory failure
         * and to take the appropriate next step.
         */
         
        pbistFail();

    } 
	
    /* Disable PBIST clocks and disable memory self-test mode */
    pbistStop();	

/* USER CODE BEGIN (27) */
/* USER CODE END */

    /* Make sure that the CPU self-test controller can actually detect a fault inside CPU */
#if !(_IAR_DEBUG==1)
    stcSelfCheck();
#else
    afterSTC();
#endif

/* USER CODE BEGIN (28) */
/* USER CODE END */
}

void afterSTC(void)
{

/* USER CODE BEGIN (29) */
#if !(_IAR_DEBUG==1)
    /* Note:
     * Certain debug operations place the CPU in a halting debug state where the code execution is halted.
     * Because halting debug events are asynchronous, there is a possibility for the debug requests to cause
     * loss of lockstep. CCM-R4F will disable upon detection of halting debug requests. Core compare error will
     * not be generated and flags will not update. A CPU reset is needed to ensure the CPUs are again in
     * lockstep and will also re-enable the CCM-R4F.
     *
     * So ccmSelfCheck() should be run only in released software;
     */
/* USER CODE END */

    /* Make sure that CCM-R4F is working as expected.
     * This function puts the CCM-R4F module through its self-test modes.
     * It ensures that the CCM-R4F is indeed capable of detecting a CPU mismatch,
     * and is also capable of indicating a mismatch error to the ESM.
     */
    ccmSelfCheck();

/* USER CODE BEGIN (30) */
#endif
/* USER CODE END */

/* USER CODE BEGIN (31) */
/* USER CODE END */

    /* Disable RAM ECC before doing PBIST for Main RAM */
    _coreDisableRamEcc_();
    
    /* Run PBIST on CPU RAM.
     * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
     * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
     * device datasheet.
     */
    pbistRun(0x00100020U, /* ESRAM Single Port PBIST */
             (uint32)PBIST_March13N_SP);

/* USER CODE BEGIN (32) */
/* USER CODE END */

    /* Wait for PBIST for CPU RAM to be completed */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while(pbistIsTestCompleted() != TRUE)
    { 
    }/* Wait */                 
    

/* USER CODE BEGIN (33) */
/* USER CODE END */
    
    /* Check if CPU RAM passed the self-test */
    if( pbistIsTestPassed() != TRUE)
    {
        /* CPU RAM failed the self-test.
         * Need custom handler to check the memory failure
         * and to take the appropriate next step.
         */
/* USER CODE BEGIN (34) */
/* USER CODE END */
         
        pbistFail();
        
/* USER CODE BEGIN (35) */
/* USER CODE END */
    }

/* USER CODE BEGIN (36) */
/* USER CODE END */

    /* Disable PBIST clocks and disable memory self-test mode */
    pbistStop();


/* USER CODE BEGIN (37) */
/* USER CODE END */


    /* Initialize CPU RAM.
     * This function uses the system module's hardware for auto-initialization of memories and their
     * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
     * Hence the value 0x1 passed to the function.
     * This function will initialize the entire CPU RAM and the corresponding ECC locations.
     */
    memoryInit(0x1U);

/* USER CODE BEGIN (38) */
/* USER CODE END */

    /* Enable ECC checking for TCRAM accesses.
     * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
     */
    _coreEnableRamEcc_();

/* USER CODE BEGIN (39) */
/* USER CODE END */

    /* Start PBIST on all dual-port memories */
    /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories.
       PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
     */
    pbistRun(  (uint32)0x00000000U    /* EMAC RAM */
             | (uint32)0x00000000U    /* USB RAM */
             | (uint32)0x00000800U    /* DMA RAM */
             | (uint32)0x00000200U    /* VIM RAM */
             | (uint32)0x00000040U    /* MIBSPI1 RAM */
             | (uint32)0x00000080U    /* MIBSPI3 RAM */
             | (uint32)0x00000100U    /* MIBSPI5 RAM */
             | (uint32)0x00000000U    /* CAN1 RAM */
             | (uint32)0x00000000U    /* CAN2 RAM */
             | (uint32)0x00000000U    /* CAN3 RAM */
             | (uint32)0x00000400U    /* ADC1 RAM */
             | (uint32)0x00000000U    /* ADC2 RAM */
             | (uint32)0x00001000U    /* HET1 RAM */
             | (uint32)0x00040000U    /* HET2 RAM */
             | (uint32)0x00000000U    /* HTU1 RAM */
             | (uint32)0x00000000U    /* HTU2 RAM */
             | (uint32)0x00000000U    /* RTP RAM */
             | (uint32)0x00000000U    /* FRAY RAM */
             ,(uint32) PBIST_March13N_DP);

/* USER CODE BEGIN (40) */
/* USER CODE END */
/* USER CODE BEGIN (43) */
/* USER CODE END */

    /* Wait for PBIST for CPU RAM to be completed */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while(pbistIsTestCompleted() != TRUE)
    {
    }/* Wait */


/* USER CODE BEGIN (44) */
/* USER CODE END */

    /* Check if CPU RAM passed the self-test */
    if( pbistIsTestPassed() != TRUE)
    {

/* USER CODE BEGIN (45) */
/* USER CODE END */

        /* CPU RAM failed the self-test.
         * Need custom handler to check the memory failure
         * and to take the appropriate next step.
         */
/* USER CODE BEGIN (46) */
/* USER CODE END */

        pbistFail();

/* USER CODE BEGIN (47) */
/* USER CODE END */
    }

/* USER CODE BEGIN (48) */
/* USER CODE END */

    /* Disable PBIST clocks and disable memory self-test mode */
    pbistStop();

/* USER CODE BEGIN (55) */
/* USER CODE END */

    /* Release the MibSPI1 modules from local reset.
     * This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
     */
    mibspiREG1->GCR0 = 0x1U;

    /* Release the MibSPI3 modules from local reset.
     * This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
     */
    mibspiREG3->GCR0 = 0x1U;

    /* Release the MibSPI5 modules from local reset.
     * This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
     */
    mibspiREG5->GCR0 = 0x1U;

/* USER CODE BEGIN (56) */
/* USER CODE END */

    /* Enable parity on selected RAMs */
    enableParity();

    /* Initialize all on-chip SRAMs except for MibSPIx RAMs
     * The MibSPIx modules have their own auto-initialization mechanism which is triggered
     * as soon as the modules are brought out of local reset.
     */
    /* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
     */
    /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
              Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
     */
    memoryInit( (uint32)((uint32)1U << 1U)    /* DMA RAM */
              | (uint32)((uint32)1U << 2U)    /* VIM RAM */
              | (uint32)((uint32)0U << 5U)    /* CAN1 RAM */
              | (uint32)((uint32)0U << 6U)    /* CAN2 RAM */
              | (uint32)((uint32)0U << 10U)   /* CAN3 RAM */
              | (uint32)((uint32)1U << 8U)    /* ADC1 RAM */
              | (uint32)((uint32)0U << 14U)   /* ADC2 RAM */
              | (uint32)((uint32)1U << 3U)    /* HET1 RAM */
              | (uint32)((uint32)0U << 4U)    /* HTU1 RAM */
              | (uint32)((uint32)1U << 15U)   /* HET2 RAM */
              | (uint32)((uint32)0U << 16U)   /* HTU2 RAM */
              );

    /* Disable parity */
    disableParity();

    /* Test the parity protection mechanism for peripheral RAMs
       NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
                 Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
    */

/* USER CODE BEGIN (57) */
/* USER CODE END */

    het1ParityCheck();

/* USER CODE BEGIN (59) */
/* USER CODE END */

    het2ParityCheck();

/* USER CODE BEGIN (61) */
/* USER CODE END */

    adc1ParityCheck();

/* USER CODE BEGIN (66) */
/* USER CODE END */

    vimParityCheck();

/* USER CODE BEGIN (67) */
/* USER CODE END */

    dmaParityCheck();


/* USER CODE BEGIN (68) */
/* USER CODE END */

/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
    {
    }/* Wait */
    /* wait for MibSPI1 RAM to complete initialization */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
    { 
    }/* Wait */                 
    /* wait for MibSPI3 RAM to complete initialization */ 
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
    {
    }/* Wait */
    /* wait for MibSPI5 RAM to complete initialization */

/* USER CODE BEGIN (69) */
/* USER CODE END */

    mibspi1ParityCheck();

/* USER CODE BEGIN (70) */
/* USER CODE END */

    mibspi3ParityCheck();

/* USER CODE BEGIN (71) */
/* USER CODE END */

    mibspi5ParityCheck();


/* USER CODE BEGIN (72) */
/* USER CODE END */

    /* Enable IRQ offset via Vic controller */
    _coreEnableIrqVicOffset_();


/* USER CODE BEGIN (73) */
/* USER CODE END */

    /* Initialize VIM table */
    vimInit();

/* USER CODE BEGIN (74) */
/* USER CODE END */

    /* Configure system response to error conditions signaled to the ESM group1 */
    /* This function can be configured from the ESM tab of HALCoGen */
    esmInit();
/* USER CODE BEGIN (75) */
/* USER CODE END */

    /* call the application */
    __cmain();
/* USER CODE BEGIN (77) */
/* USER CODE END */
}

/* USER CODE BEGIN (78) */
/* USER CODE END */
/** @fn void handlePLLLockFail(void)
*   @brief This function handles PLL lock fail.
*/
void handlePLLLockFail(void)
{
/* USER CODE BEGIN (79) */
/* USER CODE END */
	while(1)
	{

	}
/* USER CODE BEGIN (80) */
/* USER CODE END */
}
/* USER CODE BEGIN (81) */
/* USER CODE END */

0 jagadish gundavarapu over 2 years ago in reply to Chunyan Li

TI__Guru* 76926 points

Hi Chunyan,

Thanks for sharing details, i will reproduce the issue at my end and see the behavior. Please expect some delay.

Thanks & regards,
Jagadish.

0 jagadish gundavarapu over 2 years ago in reply to jagadish gundavarapu

TI__Guru* 76926 points

Hi Chunyan,

I tested the issue you mentioned in the RM46 as i don't have the RM44 board. Because two boards have almost the same hardware.

In RM46 i don't find the issue you mentioned, i mean i can be able to get the FE error for both with multi-buffer and without multi-buffer modes.

I created one simple example to test this behavior. I will provide the code and test procedure i followed so please do the same at your end on your RM44 and let me know the results.

1. First i created one SCI example with 9600 baudrate.

And also i enabled the interrupts you mentioned

2. Now i enabled the multi-buffered mode in the code using the following function

3. Now i just run the code in debug mode.

4. And now to create frame error i gave baudrate mismatch in terminal side.

the below is the configuration in terminal side

5. After this i send one character from terminal to the board over UART

6. And this hits the break point i set in the starting of the function "linHighLevelInterrupt"

7. And now you can see the flags that are set

As you can see their bit 26th got SET, that is frame error.

So, my request to you is please create similar example on your side and see the behavior based on that we can confirm whether the FE bits are operating in RM44 or not in multi-buffered mode.

Here is the code i tested:

SCI_LIN_MulitBuffer_Mode_test_with_FE_RM46.zip

Thanks & regards,
Jagadish.

0 Chunyan Li over 2 years ago in reply to jagadish gundavarapu

Prodigy 30 points

Hi Jagadish,
Thanks for your reply.
I will compare my code with yours and make adjustments if necessary. I will contact you when I am finished testing the new code. Thank you for your help, and talk to you soon!
Best regards,
Chunyan

+1 Chunyan Li over 2 years ago in reply to Chunyan Li

Prodigy 30 points

Hi Jagadish,

I have discovered the reason why the microcontroller gets stuck at the LIN ISR (linLowLevelInterrupt) with the Receive flag (INTVECT1 = 11 / Receive):
I have read the receiving byte from the RX register in multi-buffer mode, which does not reset the RXRDY flag.
Instead, the LINRD0 / LINRD1 register shall be read since the RXRDY flag can only be cleared in multi-buffer mode by reading from the LINRD0 / LINRD1 register, depending on the LENGTH setting.

Interestingly, the SCIFORMAT->LENGTH register not only sets the receive trigger level but also determines the size of the buffer, unlike the standard UART 16550A.
In our project, the frame size is flexible, so LENGTH needs to be set to 1 byte. Furthermore, we need a method to prevent the loss of received data at high rates.
Unfortunately, the design of the multi-buffer mode (where LENGTH equals the size of the buffer) cannot meet our requirements. In this case, we will not operate LIN/SCI in multi-buffer mode.

Furthermore, the structure generated by HalCoGen is a bit confusing for little-endian microcontrollers:
typedef volatile struct linBase
{
uint32 GCR0; /**< 0x0000: Global control register 0 */
uint32 GCR1; /**< 0x0004: Global control register 1 */
uint32 GCR2; /**< 0x0008: Global control register 2 */
uint32 SETINT; /**< 0x000C: Set interrupt enable register */
uint32 CLEARINT; /**< 0x0010: Clear interrupt enable register */
uint32 SETINTLVL; /**< 0x0014: Set interrupt level register */
uint32 CLEARINTLVL; /**< 0x0018: Set interrupt level register */
uint32 FLR; /**< 0x001C: interrupt flag register */
uint32 INTVECT0; /**< 0x0020: interrupt vector Offset 0 */
uint32 INTVECT1; /**< 0x0024: interrupt vector Offset 1 */
uint32 FORMAT; /**< 0x0028: Format Control Register */
uint32 BRS; /**< 0x002C: Baud rate selection register */
uint32 ED; /**< 0x0030: Emulation register */
uint32 RD; /**< 0x0034: Receive data register */
uint32 TD; /**< 0x0038: Transmit data register */
uint32 PIO0; /**< 0x003C: Pin function register */
uint32 PIO1; /**< 0x0040: Pin direction register */
uint32 PIO2; /**< 0x0044: Pin data in register */
uint32 PIO3; /**< 0x0048: Pin data out register */
uint32 PIO4; /**< 0x004C: Pin data set register */
uint32 PIO5; /**< 0x0050: Pin data clr register */
uint32 PIO6; /**< 0x0054: Pin open drain output enable register */
uint32 PIO7; /**< 0x0058: Pin pullup/pulldown disable register */
uint32 PIO8; /**< 0x005C: Pin pullup/pulldown selection register */
uint32 COMP; /**< 0x0060: Compare register */
uint8 RDx[8U]; /**< 0x0064-0x0068: RX buffer register */
uint32 MASK; /**< 0x006C: Mask register */
uint32 ID; /**< 0x0070: Identification Register */
uint8 TDx[8U]; /**< 0x0074-0x0078: TX buffer register */
uint32 MBRSR; /**< 0x007C: Maximum baud rate selection register */
uint32 rsvd1[4U]; /**< 0x0080 - 0x8C: Reserved */
uint32 IODFTCTRL; /**< 0x0090: IODFT loopback register */
} linBASE_t;

For microcontroller RM44L920:
RDx[0] corresponds to Receive buffer 3
RDx[1] corresponds to Receive buffer 2
RDx[2] corresponds to Receive buffer 1
RDx[3] corresponds to Receive buffer 0
RDx[4] corresponds to Receive buffer 7
RDx[5] corresponds to Receive buffer 6
RDx[6] corresponds to Receive buffer 5
RDx[7] corresponds to Receive buffer 4
The received byte should be read from RDx[3].

Many thanks for your support!

Best regards,
Chunyan

Arm-based microcontrollers

Arm-based microcontrollers forum

SCI/LIN multi-buffered mode