AM2732: How to config the watchdog RTI clock value?

Hi team,

In mcu_plus_sdk_am273x_08_05_00_24, what's the default value for watchdog RTI input clock(divider default is 0X777, source = 0x222, should be 25MHz?)? 

Then I use API to change the divider, with below config, we can see the divider is set to 0xfff.

SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId_MSS_WDT,SOC_RcmPeripheralClockSource_SYS_CLK,12500000);

But, I use below API to change the divider to 2MHz, with below config, we can see the divider is set to 0x333. Not matching the 2MHz.(it look likes overflow)

SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId_MSS_WDT,SOC_RcmPeripheralClockSource_SYS_CLK,2000000);

Is the data range for this input clock divider 0x0-0xF? In TRM, this is a 12bit register, so need your confirm here.

Thanks,

Wesley