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MSPM0G3507: ADC

Jonathan Valvano
Intellectual 260 points
Part Number: MSPM0G3507
Other Parts Discussed in Thread: SYSCONFIG

The TRM for the MSPM0G3507 lists FRANGE=7 for bus clock 40-48MHz

However, my ADC code seems to work with a bus clock of 80MHz. The data sheet also lists the ADC0/ADC1 as both PD1 and PD0.

1) Is the ADC in PD0 so the CPU clock of 80 MHz is actually 40MHz at the ADC?

2) Is the ADC in PD1, so the CPU clock of 80 MHz is actually 80MHz at the ADC, but FRANGE=7 is correct?

thanks

  • 0
    TI__Mastermind 25570 points

    Hi Jonathan,

    Which version of the SDK are you using? I recommend updating to the latest MSPM0 SDK v 1.10.0.05.

    The ADC is maxed at 48MHz, and can be either PD0 and PD1. PD0 will use ULPCLK and PD1 will use HFCLK/MCLK. ULPCLK is maxed at 40MHz, so if your MCLK is running at 80MHz you will need to clock divide the ULPCLK to 40MHz.

    Regards,

    Luke

  • 0 in reply to Luke Ledbetter
    Intellectual 260 points

    Thanks, how do I tell if the ADC is PD0 or PD1? The MSPM0G3507 data sheet shows it in orange. Does this mean CPU access is PD1? By studying TimerG0 (PD0) and TimerG7 (PD1), I see SYSOSC is 40MHz for PD0 and 80MHz for PD1, when CPU is running at 80MHz.

    I'm not using SysConfig. Currently I have MSPM0 SDK v 1.10.0.03, I will upgrade to MSPM0 SDK v 1.10.0.05.

    My ULPCLK has a divide by 2 (40MHz), but MCLK has no divide (80MHz).  So, your recommendation is to use ULPCLK for the ADC, correct? However, if the ADC is in PD0, won't SYSOSC also be 40MHz? My ADC code seems to work with either ULPCLK or SYSOSC settings in SAMPCLK field of CLKCFG register.

    PS, I'm writing a book and want to describe the ADC correctly.

    Thanks

  • 0 in reply to Jonathan Valvano
    TI__Mastermind 25570 points

    Hi Jonathan,

    I probably created some confusion with my response so let me back up here and explain in better detail.

    The ADC peripheral can operate with a clock source up to 48 MHz. There are 3 potential options for the clock source as shown in the block diagram, each clock source will change with power domain the ADC operates from (generally speaking).

    1. When using ULPCLK your operation range is up to 40MHz and the ADC will be on PD0.
    2. When using SYSOSC your operation range will be 4MHz or 32MHz and the ADC will be on PD1.
    3. When using HFCLK your operation range is up to 48 MHz and the ADC will be on PD1.

    To fully understand the trade offs it is important to look at the Supported Functionality by Operating Mode table in the MSPM0G TRM.

    When peripherals have a BUSCLK it refers to the clock on their power domain. All peripherals on Power Domain 0 will use ULPCLK and all peripherals on Power Domain 1 will use MCLK.

    So the ADC is special, it can be either PD0 or PD1 depending on the clock source given.

    My recommendation is to use ULPCLK if you need to run in lower power modes and you won't need faster than 40MHz. Use HFCLK if you want to go faster than 40 MHz. Use SYSOSC if you are running ULPCLK at a different frequency but still need a faster clock for ADC sampling. Of course this is a general recommendation and there could always be exceptions depending on your application.

    Regards,

    Luke