AM2634: ADC interrupts are not getting triggered when configured AD Exclusive area implementation as per TI manual

Hi Aswathy jayagopi

The ADC source code itself looks weird. Because the MCAL's exclusive area implementation is simply disabling "Global interrupts" by writing 1 to the IRQ bit in the CPSR register. So, if ADC interrupts are triggered inside the critical section that's a problem in interrupt mode.

Aswathy jayagopi said:

When we modified exclusive area implementation as NONE, that means no interrupts are disabled or enabled, that time ADC interrupts are getting triggered.

I guess my above explanation explains why interrupts are getting triggered when implementation is chosen as NONE.

Let me check with the Author if this is an issue or any updates/fixes are done.

Thanks,
G Kowshik

Could you please suggest the recommended exclusive area implementation for ADC?

because in continuous mode, we get interrupt trigger continuously. In this case we have to configure the critical sections correctly otherwise it will end up with OS error.

Hi Aswathy,

Allow me some time to check on this with the module owner and come back. He's been OOO for last few days. I will have some answer by today EOD or tomorrow early hours.

Thanks

Hi Aswathy,

Question 1:
As per ADC manual, All adc interrupts needs to be suspended in the critical section.
when we suspended all the interrupts inside ADC exclusive area, ADC Interrupts are also not getting triggered.

we found in the Adc.c that ADC Start group conversion is happening inside the critical area and we suspended in the configuration as well.

Is it because of the disabling of interrupts inside critical area? Could you please suggest how to implement critical area for ADC?

==>
Would you please lets know, how your disabling all the interrupts.
Here we would suggest disable or enable the XBAR interrupts, that are assigned for ADC module.

Can pls check the values provided the register "CONTROLSS_ADC0_CFG_ADCINTFLG". The address is "0x502C0006h".
This register indicates the ADC Interrupt has occured or not.

Question 2:

When we modified exclusive area implementation as NONE, that means no interrupts are disabled or enabled, that time ADC interrupts are getting triggered.

But when we start the continuous mode conversion, software always shows OS error and not getting any ADC Interrupt notification, is there anything we need to consider for ADC continuous mode operation?

Do we need to stop the conversion at any time?

==>
In continous mode there would be chance interrupts getting overflow.

We would like to know, whether CAT1 or CAT2 ISR is used. If CAT2, we would like to know how the ISR implementation is done.

Question 1 ==>we tried with disabling the interrupt which is configured in the OS for ADC. in that time also we are not getting any interrupts.

I will check the values in the given register and come back.

Question 2 ==> we configured CAT2 interrupt. In OS we configured interrupt with source number 147 and gave special function name as implemented in the Adc_Irq.c.  we get call to the group notification function configured in Adc from ISR handler in Adc_Irq.c.

Thank you!!

Hi Aswathy,

I am working with the ADC expert to get the answers for above. Meanwhile can you please share the register values please?

Thanks

Hi Team,

I have checked the value of registers before exiting the critical area. and value is Zero only.

One more observation: If we stop the conversion of ADC group with continuous mode after certain period of time, in that case there is no OS error. I suspect interrupts getting overflow. 

In critical Area, disabled only ADC interrupt. 

Thanks 

Hello Kowshik,

One more update.

if critical area is implemented as NONE- then only buffer will update.

if disable ADC interrupts inside critical area, then buffer won't get update.

I hope I will get a solution as soon as earlier.

Thanks

Hi Aswathy,

We are analyzing it and will get back to you.

Thanks

Hello team,

Any update on this issue? 

Many thanks,

Aswathy J G

Hi Aswathy,

"if disable ADC interrupts inside critical area, then buffer won't get update"
ADC interrupts, which interrupts are getting disabled here (ADC internal interrupts or cross bar interrupts).
We suggest disabling the ADC cross bar interrupts configured, here.

In continuous mode, we check the issue to reproduce. We are not able to reproduce here.

Thanks

Hi Mudit,

I disabled ADC crossbar interrupts only. By using exclusive area implementation in RTE, we can disable the interrupts which we configured for a module. I just disabled the crossbar interrupts configured for ADC.

If I am disabling ADC crossbar interrupts and starting the continuous conversion, then i am not getting any ADC interrupts. - Checked in Adc_Irq.c with breakpoint and configured ADC notification as well. Notification also not getting in software.

- I have configured CAT2 interrupt as explained in the same thread and configured ADC notification as well.

-If critical area configured as NONE, then ADC interrupts getting triggered for continuous conversion with same test setup. Only change is the value of critical area.

- With exclusive area as NONE, Interrupts overflow occurred after some time.

I have already shared register values also in the same thread.

Could you please explain the critical area implementation? and any other preconditions for continuous mode conversion.?

Thanks and Regards

Aswathy

Hi Aswathy,

can you please reach out to your TI field representative, so that we ca have the debug call?

Thanks 

Mudit Bhansali

Gudimetla kowshik Hello Kowshik,

Can we have a small call for understanding and solving this issue? Could you please provide a suitable time for the call?

Thanks 

Aswathy J G

Sure , we can have a call tomorrow at 2:30pm (INDIA time), if this works fine for you.

Thanks

Mudit Bhansali

Hi,

Could you please share your mail id, I will send an invitation for this session.

Thank you

Aswathy  J G

Hello Aswathy,

As discussed, we are able to enable ADC conversion results, using direct register setting of cross bar interrupts.

Please find the register details to verify.
Register:
To enable ADC Interrupt:
VIM_INTR_EN_SET_4 Register
Address:0x50F00488h

To disable ADC Interrupt:
VIM_INTR_EN_SET_4 Register
Address:0x50F0048Ch

The issue could be with OS module. Please confirm the same.

Regards,

Pratik

Register name is corrected here against previous comment.
Please find the register details to verify.
Register:
To enable ADC Interrupt:
VIM_INTR_EN_SET_4 Register
Address:0x50F00488h

To disable ADC Interrupt:
VIM_INTER_EN_CLR_4 Register
Address:0x50F0048Ch

Regards,

Pratik

Hello Pratik,

Thank you for sharing register names.

1. I have tried with the function you shared for direct register setting of cross bar interrupts.

VIM_INTR_EN_SET_4 Register
Address:0x50F00488h

VIM_INTER_EN_CLR_4 Register
Address:0x50F0048Ch

The register values of both the given register have no change before and after the call of these enable /disable functions, it always same and it is as below

value is always 0x0001 0008.

it remains same while entering and leaving the critical area.

2. I have tried with OS disable/enable interrupt source function,

when enter into critical area value of both registers become 0x0001 0000

after leaving critical area value becomes 0x0001 0008

these are observations.

From my understanding, these register vales supposed to be updated while entering and leaving the critical area. but that is not happening with direct setting.

Please confirm from your side.

Thank you

Aswathy j g

Hello Aswathy,

Enable and Disable is working fine at our end.

The Functionality of register setting and clearing looks fine with OS.

Please verify once by setting registers directly like below:
----------------------------------------------------------------------
void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_0()
{
// AppUtils_SchM_Enter_EXCLUSIVE_AREA_0();
//vimDisableInterrupt(147);
//uint32 addr = 0x50F0048CU;
HW_WR_REG16(0x50F0048CU, 0x0008);
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_0()
{
//AppUtils_SchM_Exit_EXCLUSIVE_AREA_0();
//vimEnableInterrupt(147);
//uint32 addr = 0x50F00488U;
HW_WR_REG16(0x50F00488U, 0x0008);
}
----------------------------------------------------------------------

Regards,

Pratik

Hello Pratik,

Pratik Bellam said:

Enable and Disable is working fine at our end.

The Functionality of register setting and clearing looks fine with OS.

If this is correct then, the value is different with direct register setting of cross bar interrupts. The value is always 0x0001 0008 for both the registers when i checked. 

Just to clear,

1. Could you please explain the values expecting for these registers in enabling and disabling interrupts?

2. If setting and clearing ok with Os, then still we are not getting any interrupts? Could you please tell possible reasons for that issue?

Thanks 

Aswathy J G

Hello Aswathy,

If this is correct then, the value is different with direct register setting of cross bar interrupts.
The value is always 0x0001 0008 for both the registers when i checked.

==>
Works at our end, by directly setting register.

1. Could you please explain the values expecting for these registers in enabling and disabling interrupts?

==>
when enter into critical area value of registers should become 0x0000 0000
when exit into critical area value of registers should become 0x0000 0008

2. If setting and clearing ok with Os, then still we are not getting any interrupts?
Could you please tell possible reasons for that issue?

==>
We suspect, some protection is provided while writing this reigster, at your end.
Better confirm this with vector once.
We will also check, which register can be used for protection.

Please also check this register "CPSIE" status when enter or exit of critical section

Regards,

Pratik